Date: Thu, 7 May 2015 17:33:02 +0200
From: Ingo Molnar <mingo@kernel.org>
To: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ingo Molnar <mingo2.kernel.org@gmail.com>, linux-kernel@vger.kernel.org,
        Andy Lutomirski <luto@amacapital.net>, Borislav Petkov <bp@alien8.de>,
        Fenghua Yu <fenghua.yu@intel.com>, "H. Peter Anvin" <hpa@zytor.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Oleg Nesterov <oleg@redhat.com>, Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 084/208] x86/fpu: Rename xsave.header::xstate_bv to
 'xfeatures'
Message-ID: <20150507153302.GA20993@gmail.com>
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* Dave Hansen <dave.hansen@linux.intel.com> wrote:

> > Btw., regarding XCR0.PKRU: that enables 'Protection Keys' in the 
> > PTE format. What's the main purpose of these keys? They seem to 
> > duplicate the read/write bits in the PTE, with the exception that 
> > they don't impact instruction fetches. So is this used to allow 
> > user-space to execute but otherwise not read instructions?
> > 
> > Or some other purpose I missed?
> 
> You can change the permissions of a given key with writes to the 
> register without changing the PTE.  No TLB shootdown, plus the 
> permission changes are local to the CPU thread.

interesting ... where are we doing that? kmap_atomic() is the only 
place I can think of in the kernel, but there we are already skipping 
the TLB shootdown by doing an INVLPG.

> I have patches today if you're interested.

I'm always interested in new CPU features ;-)

> ...
> >> We'd need to determine which fields are in the init state before we 
> >> do an xsaves.
> > 
> > Why? I don't think that's necessary.
> 
> "If RFBM[i] = 0, XSTATE_BV[i] is written as 0."

Yes, that's natural: RFBM is the combination of XCR0 (constant) and 
the 'instruction mask' (constant as well) - i.e. it's a wide bitmask 
including all our xfeatures - essentially 'xfeatures_mask' (in 
tmp.fpu).

> We need to pull XSTATE_BV in to the instruction mask when doing an 
> XSAVE* if our RFBM has bits unset that *are* set in XSTATE_BV. 
> Otherwise, we'll destroy the bits at XSAVE* time.

But why would our RFBM be narrower than any possible XSTATE_BV we 
handle? Our XCR0 is at the max.

Also, the XSTATE_BV value of the save area is immaterial when we do an 
XSAVES: all the state is in CPU registers, we want to save it to the 
save area. XSAVES will write it for us.

> It's not a problem today because the instruction mask is always -1, 
> so it always has every bit set that *MIGHT* be set in XSTATE_BV.

Yes. And why would we ever want to narrow it?

> As for the whole bit 63 thing...  It's possible and valid to have a 
> XCOMP_BV[62:0]=0 because the instruction mask only contained bits 
> that were unset in XCR0|IA32_XSS.  You need bit 63 to tell you which 
> format you are using.

So basically if you request an XSAVES to ... write nothing (XCR0 AND 
instruction mask is 0), then it will represent this as 0|1<<63 in 
XCOMP_BV?

In that case it does not matter whether the area is compacted or 
standard: nothing was saved and nothing will have to be restored, only 
the xsave header area will be accessed. Am I missing something?

Thanks,

	Ingo
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