Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752554AbbEJKpI (ORCPT ); Sun, 10 May 2015 06:45:08 -0400 Received: from down.free-electrons.com ([37.187.137.238]:54509 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752411AbbEJKpF (ORCPT ); Sun, 10 May 2015 06:45:05 -0400 Date: Sun, 10 May 2015 12:41:21 +0200 From: Maxime Ripard To: Vishnu Patekar Cc: emilio@elopez.com.ar, linus.walleij@linaro.org, robh+dt@kernel.org, hdegoede@redhat.com, wens@csie.org, jenskuske@gmail.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Message-ID: <20150510104121.GF11057@lukather> References: <1431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com> <1431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="twlwrnvElrG9k/1g" Content-Disposition: inline In-Reply-To: <1431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 34486 Lines: 1157 --twlwrnvElrG9k/1g Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Sun, May 10, 2015 at 12:16:21PM +0530, Vishnu Patekar wrote: > added the common sun8i.dtsi and "allwinner,sun8i" compatible for common > sun8i features, I've referred the h3 dtsi by Jens Kuske. > accordingly modified the sun8i-a23.dtsi and a23 dts. >=20 > I don't have a23 device, however, dts got compiled. >=20 > Signed-off-by: VishnuPatekar Once again, that patch does several unrelated things at once. > --- > arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +- > arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +- > arch/arm/boot/dts/sun8i-a23.dtsi | 432 +-------------------= --- > arch/arm/boot/dts/sun8i.dtsi | 481 ++++++++++++++++++++= ++++++ > 4 files changed, 486 insertions(+), 439 deletions(-) > create mode 100644 arch/arm/boot/dts/sun8i.dtsi >=20 > diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boo= t/dts/sun8i-a23-ippo-q8h-v1.2.dts > index dd31c53..b3f19e7 100644 > --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts > +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts > @@ -16,10 +16,6 @@ > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > - * You should have received a copy of the GNU General Public > - * License along with this file; if not, write to the Free > - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > - * MA 02110-1301 USA It removes some check patch warning (and it's not even mentionned in the commit log). > * Or, alternatively, > * > @@ -55,5 +51,5 @@ > =20 > / { > model =3D "Ippo Q8H Dual Core Tablet (v1.2)"; > - compatible =3D "ippo,q8h-v1.2", "allwinner,sun8i-a23"; > + compatible =3D "ippo,q8h-v1.2", "allwinner,sun8i", "allwinner,sun8i-a23= "; It adds a new compatible to boards. > }; > diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/= dts/sun8i-a23-ippo-q8h-v5.dts > index f5658d1..5db4010 100644 > --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts > +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts > @@ -18,10 +18,6 @@ > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > - * You should have received a copy of the GNU General Public > - * License along with this file; if not, write to the Free > - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > - * MA 02110-1301 USA > * > * Or, alternatively, > * > @@ -57,7 +53,7 @@ > =20 > / { > model =3D "Ippo Q8H Dual Core Tablet (v5)"; > - compatible =3D "ippo,q8h-v5", "allwinner,sun8i-a23"; > + compatible =3D "ippo,q8h-v5", "allwinner,sun8i", "allwinner,sun8i-a23"; > =20 > aliases { > serial0 =3D &r_uart; > diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a= 23.dtsi > index 6d6eda3..c17be9e 100644 > --- a/arch/arm/boot/dts/sun8i-a23.dtsi > +++ b/arch/arm/boot/dts/sun8i-a23.dtsi > @@ -18,10 +18,6 @@ > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > - * You should have received a copy of the GNU General Public > - * License along with this file; if not, write to the Free > - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > - * MA 02110-1301 USA > * > * Or, alternatively, > * > @@ -47,41 +43,11 @@ > * OTHER DEALINGS IN THE SOFTWARE. > */ > =20 > -#include "skeleton.dtsi" > - > -#include > - > -#include > +#include "sun8i.dtsi" > =20 > / { > - interrupt-parent =3D <&gic>; > - > - chosen { > - #address-cells =3D <1>; > - #size-cells =3D <1>; > - ranges; > - > - framebuffer@0 { > - compatible =3D "allwinner,simple-framebuffer", > - "simple-framebuffer"; > - allwinner,pipeline =3D "de_be0-lcd0"; > - clocks =3D <&pll6 0>; > - status =3D "disabled"; > - }; > - }; > - > - timer { > - compatible =3D "arm,armv7-timer"; > - interrupts =3D , > - , > - , > - ; > - clock-frequency =3D <24000000>; > - arm,cpu-registers-not-fw-configured; > - }; > - > cpus { > - enable-method =3D "allwinner,sun8i-a23"; > + enable-method =3D "allwinner,sun8i"; It updates a CPU enable method. > #address-cells =3D <1>; > #size-cells =3D <0>; > =20 > @@ -103,32 +69,6 @@ > }; > =20 > clocks { > - #address-cells =3D <1>; > - #size-cells =3D <1>; > - ranges; > - > - osc24M: osc24M_clk { > - #clock-cells =3D <0>; > - compatible =3D "fixed-clock"; > - clock-frequency =3D <24000000>; > - clock-output-names =3D "osc24M"; > - }; > - > - osc32k: osc32k_clk { > - #clock-cells =3D <0>; > - compatible =3D "fixed-clock"; > - clock-frequency =3D <32768>; > - clock-output-names =3D "osc32k"; > - }; > - > - pll1: clk@01c20000 { > - #clock-cells =3D <0>; > - compatible =3D "allwinner,sun8i-a23-pll1-clk"; > - reg =3D <0x01c20000 0x4>; > - clocks =3D <&osc24M>; > - clock-output-names =3D "pll1"; > - }; > - > /* dummy clock until actually implemented */ > pll5: pll5_clk { > #clock-cells =3D <0>; > @@ -137,29 +77,6 @@ > clock-output-names =3D "pll5"; > }; > =20 > - pll6: clk@01c20028 { > - #clock-cells =3D <1>; > - compatible =3D "allwinner,sun6i-a31-pll6-clk"; > - reg =3D <0x01c20028 0x4>; > - clocks =3D <&osc24M>; > - clock-output-names =3D "pll6", "pll6x2"; > - }; > - > - cpu: cpu_clk@01c20050 { > - #clock-cells =3D <0>; > - compatible =3D "allwinner,sun4i-a10-cpu-clk"; > - reg =3D <0x01c20050 0x4>; > - > - /* > - * PLL1 is listed twice here. > - * While it looks suspicious, it's actually documented > - * that way both in the datasheet and in the code from > - * Allwinner. > - */ > - clocks =3D <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; > - clock-output-names =3D "cpu"; > - }; > - > axi: axi_clk@01c20050 { > #clock-cells =3D <0>; > compatible =3D "allwinner,sun8i-a23-axi-clk"; > @@ -168,22 +85,6 @@ > clock-output-names =3D "axi"; > }; > =20 > - ahb1: ahb1_clk@01c20054 { > - #clock-cells =3D <0>; > - compatible =3D "allwinner,sun6i-a31-ahb1-clk"; > - reg =3D <0x01c20054 0x4>; > - clocks =3D <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; > - clock-output-names =3D "ahb1"; > - }; > - > - apb1: apb1_clk@01c20054 { > - #clock-cells =3D <0>; > - compatible =3D "allwinner,sun4i-a10-apb0-clk"; > - reg =3D <0x01c20054 0x4>; > - clocks =3D <&ahb1>; > - clock-output-names =3D "apb1"; > - }; > - > ahb1_gates: clk@01c20060 { > #clock-cells =3D <1>; > compatible =3D "allwinner,sun8i-a23-ahb1-gates-clk"; > @@ -228,36 +129,6 @@ > "apb2_uart3", "apb2_uart4"; > }; > =20 > - mmc0_clk: clk@01c20088 { > - #clock-cells =3D <1>; > - compatible =3D "allwinner,sun4i-a10-mmc-clk"; > - reg =3D <0x01c20088 0x4>; > - clocks =3D <&osc24M>, <&pll6 0>; > - clock-output-names =3D "mmc0", > - "mmc0_output", > - "mmc0_sample"; > - }; > - > - mmc1_clk: clk@01c2008c { > - #clock-cells =3D <1>; > - compatible =3D "allwinner,sun4i-a10-mmc-clk"; > - reg =3D <0x01c2008c 0x4>; > - clocks =3D <&osc24M>, <&pll6 0>; > - clock-output-names =3D "mmc1", > - "mmc1_output", > - "mmc1_sample"; > - }; > - > - mmc2_clk: clk@01c20090 { > - #clock-cells =3D <1>; > - compatible =3D "allwinner,sun4i-a10-mmc-clk"; > - reg =3D <0x01c20090 0x4>; > - clocks =3D <&osc24M>, <&pll6 0>; > - clock-output-names =3D "mmc2", > - "mmc2_output", > - "mmc2_sample"; > - }; > - > mbus_clk: clk@01c2015c { > #clock-cells =3D <0>; > compatible =3D "allwinner,sun8i-a23-mbus-clk"; > @@ -268,11 +139,6 @@ > }; > =20 > soc@01c00000 { > - compatible =3D "simple-bus"; > - #address-cells =3D <1>; > - #size-cells =3D <1>; > - ranges; > - > dma: dma-controller@01c02000 { > compatible =3D "allwinner,sun8i-a23-dma"; > reg =3D <0x01c02000 0x1000>; > @@ -282,75 +148,12 @@ > #dma-cells =3D <1>; > }; > =20 > - mmc0: mmc@01c0f000 { > - compatible =3D "allwinner,sun5i-a13-mmc"; > - reg =3D <0x01c0f000 0x1000>; > - clocks =3D <&ahb1_gates 8>, > - <&mmc0_clk 0>, > - <&mmc0_clk 1>, > - <&mmc0_clk 2>; > - clock-names =3D "ahb", > - "mmc", > - "output", > - "sample"; > - resets =3D <&ahb1_rst 8>; > - reset-names =3D "ahb"; > - interrupts =3D ; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > - mmc1: mmc@01c10000 { > - compatible =3D "allwinner,sun5i-a13-mmc"; > - reg =3D <0x01c10000 0x1000>; > - clocks =3D <&ahb1_gates 9>, > - <&mmc1_clk 0>, > - <&mmc1_clk 1>, > - <&mmc1_clk 2>; > - clock-names =3D "ahb", > - "mmc", > - "output", > - "sample"; > - resets =3D <&ahb1_rst 9>; > - reset-names =3D "ahb"; > - interrupts =3D ; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > - mmc2: mmc@01c11000 { > - compatible =3D "allwinner,sun5i-a13-mmc"; > - reg =3D <0x01c11000 0x1000>; > - clocks =3D <&ahb1_gates 10>, > - <&mmc2_clk 0>, > - <&mmc2_clk 1>, > - <&mmc2_clk 2>; > - clock-names =3D "ahb", > - "mmc", > - "output", > - "sample"; > - resets =3D <&ahb1_rst 10>; > - reset-names =3D "ahb"; > - interrupts =3D ; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > pio: pinctrl@01c20800 { > compatible =3D "allwinner,sun8i-a23-pinctrl"; > - reg =3D <0x01c20800 0x400>; > interrupts =3D , > , > ; > - clocks =3D <&apb1_gates 5>; > - gpio-controller; > - interrupt-controller; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - #gpio-cells =3D <3>; > + > =20 > uart0_pins_a: uart0@0 { > allwinner,pins =3D "PF2", "PF4"; > @@ -359,20 +162,6 @@ > allwinner,pull =3D ; > }; > =20 > - mmc0_pins_a: mmc0@0 { > - allwinner,pins =3D "PF0","PF1","PF2","PF3","PF4","PF5"; > - allwinner,function =3D "mmc0"; > - allwinner,drive =3D ; > - allwinner,pull =3D ; > - }; > - > - mmc1_pins_a: mmc1@0 { > - allwinner,pins =3D "PG0","PG1","PG2","PG3","PG4","PG5"; > - allwinner,function =3D "mmc1"; > - allwinner,drive =3D ; > - allwinner,pull =3D ; > - }; > - > i2c0_pins_a: i2c0@0 { > allwinner,pins =3D "PH2", "PH3"; > allwinner,function =3D "i2c0"; > @@ -395,38 +184,6 @@ > }; > }; > =20 > - ahb1_rst: reset@01c202c0 { > - #reset-cells =3D <1>; > - compatible =3D "allwinner,sun6i-a31-clock-reset"; > - reg =3D <0x01c202c0 0xc>; > - }; > - > - apb1_rst: reset@01c202d0 { > - #reset-cells =3D <1>; > - compatible =3D "allwinner,sun6i-a31-clock-reset"; > - reg =3D <0x01c202d0 0x4>; > - }; > - > - apb2_rst: reset@01c202d8 { > - #reset-cells =3D <1>; > - compatible =3D "allwinner,sun6i-a31-clock-reset"; > - reg =3D <0x01c202d8 0x4>; > - }; > - > - timer@01c20c00 { > - compatible =3D "allwinner,sun4i-a10-timer"; > - reg =3D <0x01c20c00 0xa0>; > - interrupts =3D , > - ; > - clocks =3D <&osc24M>; > - }; > - > - wdt0: watchdog@01c20ca0 { > - compatible =3D "allwinner,sun6i-a31-wdt"; > - reg =3D <0x01c20ca0 0x20>; > - interrupts =3D ; > - }; > - > lradc: lradc@01c22800 { > compatible =3D "allwinner,sun4i-a10-lradc-keys"; > reg =3D <0x01c22800 0x100>; > @@ -434,58 +191,6 @@ > status =3D "disabled"; > }; > =20 > - uart0: serial@01c28000 { > - compatible =3D "snps,dw-apb-uart"; > - reg =3D <0x01c28000 0x400>; > - interrupts =3D ; > - reg-shift =3D <2>; > - reg-io-width =3D <4>; > - clocks =3D <&apb2_gates 16>; > - resets =3D <&apb2_rst 16>; > - dmas =3D <&dma 6>, <&dma 6>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > - > - uart1: serial@01c28400 { > - compatible =3D "snps,dw-apb-uart"; > - reg =3D <0x01c28400 0x400>; > - interrupts =3D ; > - reg-shift =3D <2>; > - reg-io-width =3D <4>; > - clocks =3D <&apb2_gates 17>; > - resets =3D <&apb2_rst 17>; > - dmas =3D <&dma 7>, <&dma 7>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > - > - uart2: serial@01c28800 { > - compatible =3D "snps,dw-apb-uart"; > - reg =3D <0x01c28800 0x400>; > - interrupts =3D ; > - reg-shift =3D <2>; > - reg-io-width =3D <4>; > - clocks =3D <&apb2_gates 18>; > - resets =3D <&apb2_rst 18>; > - dmas =3D <&dma 8>, <&dma 8>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > - > - uart3: serial@01c28c00 { > - compatible =3D "snps,dw-apb-uart"; > - reg =3D <0x01c28c00 0x400>; > - interrupts =3D ; > - reg-shift =3D <2>; > - reg-io-width =3D <4>; > - clocks =3D <&apb2_gates 19>; > - resets =3D <&apb2_rst 19>; > - dmas =3D <&dma 9>, <&dma 9>; > - dma-names =3D "rx", "tx"; > - status =3D "disabled"; > - }; > - > uart4: serial@01c29000 { > compatible =3D "snps,dw-apb-uart"; > reg =3D <0x01c29000 0x400>; > @@ -498,136 +203,5 @@ > dma-names =3D "rx", "tx"; > status =3D "disabled"; > }; > - > - i2c0: i2c@01c2ac00 { > - compatible =3D "allwinner,sun6i-a31-i2c"; > - reg =3D <0x01c2ac00 0x400>; > - interrupts =3D ; > - clocks =3D <&apb2_gates 0>; > - resets =3D <&apb2_rst 0>; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > - i2c1: i2c@01c2b000 { > - compatible =3D "allwinner,sun6i-a31-i2c"; > - reg =3D <0x01c2b000 0x400>; > - interrupts =3D ; > - clocks =3D <&apb2_gates 1>; > - resets =3D <&apb2_rst 1>; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > - i2c2: i2c@01c2b400 { > - compatible =3D "allwinner,sun6i-a31-i2c"; > - reg =3D <0x01c2b400 0x400>; > - interrupts =3D ; > - clocks =3D <&apb2_gates 2>; > - resets =3D <&apb2_rst 2>; > - status =3D "disabled"; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - }; > - > - gic: interrupt-controller@01c81000 { > - compatible =3D "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > - reg =3D <0x01c81000 0x1000>, > - <0x01c82000 0x1000>, > - <0x01c84000 0x2000>, > - <0x01c86000 0x2000>; > - interrupt-controller; > - #interrupt-cells =3D <3>; > - interrupts =3D ; > - }; > - > - rtc: rtc@01f00000 { > - compatible =3D "allwinner,sun6i-a31-rtc"; > - reg =3D <0x01f00000 0x54>; > - interrupts =3D , > - ; > - }; > - > - prcm@01f01400 { > - compatible =3D "allwinner,sun8i-a23-prcm"; > - reg =3D <0x01f01400 0x200>; > - > - ar100: ar100_clk { > - compatible =3D "fixed-factor-clock"; > - #clock-cells =3D <0>; > - clock-div =3D <1>; > - clock-mult =3D <1>; > - clocks =3D <&osc24M>; > - clock-output-names =3D "ar100"; > - }; > - > - ahb0: ahb0_clk { > - compatible =3D "fixed-factor-clock"; > - #clock-cells =3D <0>; > - clock-div =3D <1>; > - clock-mult =3D <1>; > - clocks =3D <&ar100>; > - clock-output-names =3D "ahb0"; > - }; > - > - apb0: apb0_clk { > - compatible =3D "allwinner,sun8i-a23-apb0-clk"; > - #clock-cells =3D <0>; > - clocks =3D <&ahb0>; > - clock-output-names =3D "apb0"; > - }; > - > - apb0_gates: apb0_gates_clk { > - compatible =3D "allwinner,sun8i-a23-apb0-gates-clk"; > - #clock-cells =3D <1>; > - clocks =3D <&apb0>; > - clock-output-names =3D "apb0_pio", "apb0_timer", > - "apb0_rsb", "apb0_uart", > - "apb0_i2c"; > - }; > - > - apb0_rst: apb0_rst { > - compatible =3D "allwinner,sun6i-a31-clock-reset"; > - #reset-cells =3D <1>; > - }; > - }; > - > - cpucfg@01f01c00 { > - compatible =3D "allwinner,sun8i-a23-cpuconfig"; > - reg =3D <0x01f01c00 0x300>; > - }; > - > - r_uart: serial@01f02800 { > - compatible =3D "snps,dw-apb-uart"; > - reg =3D <0x01f02800 0x400>; > - interrupts =3D ; > - reg-shift =3D <2>; > - reg-io-width =3D <4>; > - clocks =3D <&apb0_gates 4>; > - resets =3D <&apb0_rst 4>; > - status =3D "disabled"; > - }; > - > - r_pio: pinctrl@01f02c00 { > - compatible =3D "allwinner,sun8i-a23-r-pinctrl"; > - reg =3D <0x01f02c00 0x400>; > - interrupts =3D ; > - clocks =3D <&apb0_gates 0>; > - resets =3D <&apb0_rst 0>; > - gpio-controller; > - interrupt-controller; > - #address-cells =3D <1>; > - #size-cells =3D <0>; > - #gpio-cells =3D <3>; > - > - r_uart_pins_a: r_uart@0 { > - allwinner,pins =3D "PL2", "PL3"; > - allwinner,function =3D "s_uart"; > - allwinner,drive =3D ; > - allwinner,pull =3D ; > - }; > - }; > }; > }; > diff --git a/arch/arm/boot/dts/sun8i.dtsi b/arch/arm/boot/dts/sun8i.dtsi > new file mode 100644 > index 0000000..cf481e5 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i.dtsi > @@ -0,0 +1,481 @@ > +/* > + * Copyright 2014 Chen-Yu Tsai > + * > + * Chen-Yu Tsai > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "skeleton.dtsi" > + > +#include > + > +#include > + > +/ { > + interrupt-parent =3D <&gic>; > + > + chosen { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + framebuffer@0 { > + compatible =3D "allwinner,simple-framebuffer", > + "simple-framebuffer"; > + allwinner,pipeline =3D "de_be0-lcd0"; > + clocks =3D <&pll6 0>; > + status =3D "disabled"; > + }; > + }; > + > + timer { > + compatible =3D "arm,armv7-timer"; > + interrupts =3D , > + , > + , > + ; > + clock-frequency =3D <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + clocks { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <24000000>; > + clock-output-names =3D "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <32768>; > + clock-output-names =3D "osc32k"; > + }; > + > + pll1: clk@01c20000 { > + #clock-cells =3D <0>; > + compatible =3D "allwinner,sun8i-a23-pll1-clk"; > + reg =3D <0x01c20000 0x4>; > + clocks =3D <&osc24M>; > + clock-output-names =3D "pll1"; > + }; > + > + pll6: clk@01c20028 { > + #clock-cells =3D <1>; > + compatible =3D "allwinner,sun6i-a31-pll6-clk"; > + reg =3D <0x01c20028 0x4>; > + clocks =3D <&osc24M>; > + clock-output-names =3D "pll6", "pll6x2"; > + }; > + > + cpu: cpu_clk@01c20050 { > + #clock-cells =3D <0>; > + compatible =3D "allwinner,sun4i-a10-cpu-clk"; > + reg =3D <0x01c20050 0x4>; > + > + /* > + * PLL1 is listed twice here. > + * While it looks suspicious, it's actually documented > + * that way both in the datasheet and in the code from > + * Allwinner. > + */ > + clocks =3D <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; > + clock-output-names =3D "cpu"; > + }; > + > + > + ahb1: ahb1_clk@01c20054 { > + #clock-cells =3D <0>; > + compatible =3D "allwinner,sun6i-a31-ahb1-clk"; > + reg =3D <0x01c20054 0x4>; > + clocks =3D <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; > + clock-output-names =3D "ahb1"; > + }; > + > + apb1: apb1_clk@01c20054 { > + #clock-cells =3D <0>; > + compatible =3D "allwinner,sun4i-a10-apb0-clk"; > + reg =3D <0x01c20054 0x4>; > + clocks =3D <&ahb1>; > + clock-output-names =3D "apb1"; > + }; > + > + mmc0_clk: clk@01c20088 { > + #clock-cells =3D <1>; > + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > + reg =3D <0x01c20088 0x4>; > + clocks =3D <&osc24M>, <&pll6 0>; > + clock-output-names =3D "mmc0", > + "mmc0_output", > + "mmc0_sample"; > + }; > + > + mmc1_clk: clk@01c2008c { > + #clock-cells =3D <1>; > + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > + reg =3D <0x01c2008c 0x4>; > + clocks =3D <&osc24M>, <&pll6 0>; > + clock-output-names =3D "mmc1", > + "mmc1_output", > + "mmc1_sample"; > + }; > + > + mmc2_clk: clk@01c20090 { > + #clock-cells =3D <1>; > + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > + reg =3D <0x01c20090 0x4>; > + clocks =3D <&osc24M>, <&pll6 0>; > + clock-output-names =3D "mmc2", > + "mmc2_output", > + "mmc2_sample"; > + }; > + > + }; > + > + soc@01c00000 { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + > + mmc0: mmc@01c0f000 { > + compatible =3D "allwinner,sun5i-a13-mmc"; > + reg =3D <0x01c0f000 0x1000>; > + clocks =3D <&ahb1_gates 8>, > + <&mmc0_clk 0>, > + <&mmc0_clk 1>, > + <&mmc0_clk 2>; > + clock-names =3D "ahb", > + "mmc", > + "output", > + "sample"; > + resets =3D <&ahb1_rst 8>; > + reset-names =3D "ahb"; > + interrupts =3D ; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + mmc1: mmc@01c10000 { > + compatible =3D "allwinner,sun5i-a13-mmc"; > + reg =3D <0x01c10000 0x1000>; > + clocks =3D <&ahb1_gates 9>, > + <&mmc1_clk 0>, > + <&mmc1_clk 1>, > + <&mmc1_clk 2>; > + clock-names =3D "ahb", > + "mmc", > + "output", > + "sample"; > + resets =3D <&ahb1_rst 9>; > + reset-names =3D "ahb"; > + interrupts =3D ; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + mmc2: mmc@01c11000 { > + compatible =3D "allwinner,sun5i-a13-mmc"; > + reg =3D <0x01c11000 0x1000>; > + clocks =3D <&ahb1_gates 10>, > + <&mmc2_clk 0>, > + <&mmc2_clk 1>, > + <&mmc2_clk 2>; > + clock-names =3D "ahb", > + "mmc", > + "output", > + "sample"; > + resets =3D <&ahb1_rst 10>; > + reset-names =3D "ahb"; > + interrupts =3D ; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + pio: pinctrl@01c20800 { > + reg =3D <0x01c20800 0x400>; > + clocks =3D <&apb1_gates 5>; > + gpio-controller; > + interrupt-controller; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + #gpio-cells =3D <3>; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins =3D "PF0","PF1","PF2","PF3","PF4","PF5"; > + allwinner,function =3D "mmc0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins =3D "PG0","PG1","PG2","PG3","PG4","PG5"; > + allwinner,function =3D "mmc1"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + }; > + > + ahb1_rst: reset@01c202c0 { > + #reset-cells =3D <1>; > + compatible =3D "allwinner,sun6i-a31-clock-reset"; > + reg =3D <0x01c202c0 0xc>; > + }; > + > + apb1_rst: reset@01c202d0 { > + #reset-cells =3D <1>; > + compatible =3D "allwinner,sun6i-a31-clock-reset"; > + reg =3D <0x01c202d0 0x4>; > + }; > + > + apb2_rst: reset@01c202d8 { > + #reset-cells =3D <1>; > + compatible =3D "allwinner,sun6i-a31-clock-reset"; > + reg =3D <0x01c202d8 0x4>; > + }; > + > + timer@01c20c00 { > + compatible =3D "allwinner,sun4i-a10-timer"; > + reg =3D <0x01c20c00 0xa0>; > + interrupts =3D , > + ; > + clocks =3D <&osc24M>; > + }; > + > + wdt0: watchdog@01c20ca0 { > + compatible =3D "allwinner,sun6i-a31-wdt"; > + reg =3D <0x01c20ca0 0x20>; > + interrupts =3D ; > + }; > + > + uart0: serial@01c28000 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28000 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&apb2_gates 16>; > + resets =3D <&apb2_rst 16>; > + dmas =3D <&dma 6>, <&dma 6>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > + > + uart1: serial@01c28400 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28400 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&apb2_gates 17>; > + resets =3D <&apb2_rst 17>; > + dmas =3D <&dma 7>, <&dma 7>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > + > + uart2: serial@01c28800 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28800 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&apb2_gates 18>; > + resets =3D <&apb2_rst 18>; > + dmas =3D <&dma 8>, <&dma 8>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > + > + uart3: serial@01c28c00 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28c00 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&apb2_gates 19>; > + resets =3D <&apb2_rst 19>; > + dmas =3D <&dma 9>, <&dma 9>; > + dma-names =3D "rx", "tx"; > + status =3D "disabled"; > + }; > + > + i2c0: i2c@01c2ac00 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2ac00 0x400>; > + interrupts =3D ; > + clocks =3D <&apb2_gates 0>; > + resets =3D <&apb2_rst 0>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + i2c1: i2c@01c2b000 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2b000 0x400>; > + interrupts =3D ; > + clocks =3D <&apb2_gates 1>; > + resets =3D <&apb2_rst 1>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + i2c2: i2c@01c2b400 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2b400 0x400>; > + interrupts =3D ; > + clocks =3D <&apb2_gates 2>; > + resets =3D <&apb2_rst 2>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + gic: interrupt-controller@01c81000 { > + compatible =3D "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg =3D <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + interrupts =3D ; > + }; > + > + rtc: rtc@01f00000 { > + compatible =3D "allwinner,sun6i-a31-rtc"; > + reg =3D <0x01f00000 0x54>; > + interrupts =3D , > + ; > + }; > + > + prcm@01f01400 { > + compatible =3D "allwinner,sun8i-a23-prcm"; > + reg =3D <0x01f01400 0x200>; > + > + ar100: ar100_clk { > + compatible =3D "fixed-factor-clock"; > + #clock-cells =3D <0>; > + clock-div =3D <1>; > + clock-mult =3D <1>; > + clocks =3D <&osc24M>; > + clock-output-names =3D "ar100"; > + }; > + > + ahb0: ahb0_clk { > + compatible =3D "fixed-factor-clock"; > + #clock-cells =3D <0>; > + clock-div =3D <1>; > + clock-mult =3D <1>; > + clocks =3D <&ar100>; > + clock-output-names =3D "ahb0"; > + }; > + > + apb0: apb0_clk { > + compatible =3D "allwinner,sun8i-a23-apb0-clk"; > + #clock-cells =3D <0>; > + clocks =3D <&ahb0>; > + clock-output-names =3D "apb0"; > + }; > + > + apb0_gates: apb0_gates_clk { > + compatible =3D "allwinner,sun8i-a23-apb0-gates-clk"; > + #clock-cells =3D <1>; > + clocks =3D <&apb0>; > + clock-output-names =3D "apb0_pio", "apb0_timer", > + "apb0_rsb", "apb0_uart", > + "apb0_i2c"; > + }; > + > + apb0_rst: apb0_rst { > + compatible =3D "allwinner,sun6i-a31-clock-reset"; > + #reset-cells =3D <1>; > + }; > + }; > + > + cpucfg@01f01c00 { > + compatible =3D "allwinner,sun8i-a23-cpuconfig"; > + reg =3D <0x01f01c00 0x300>; > + }; > + > + r_uart: serial@01f02800 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01f02800 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&apb0_gates 4>; > + resets =3D <&apb0_rst 4>; > + status =3D "disabled"; > + }; > + > + r_pio: pinctrl@01f02c00 { > + compatible =3D "allwinner,sun8i-a23-r-pinctrl"; > + reg =3D <0x01f02c00 0x400>; > + interrupts =3D ; > + clocks =3D <&apb0_gates 0>; > + resets =3D <&apb0_rst 0>; > + gpio-controller; > + interrupt-controller; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + #gpio-cells =3D <3>; > + > + r_uart_pins_a: r_uart@0 { > + allwinner,pins =3D "PL2", "PL3"; > + allwinner,function =3D "s_uart"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + }; > + }; > +}; And moves stuff between the A23 DTSI and sun8i DTSI. All these things should be in separate patches. Apart from that, as I told on IRC, I'd really like to have the H3 support merged and support for the A33 and H3 settle down a bit before we create such a DTSI. There's a lot of IPs that are enabled here that I'm pretty sure have never been tested and/or even apply to the H3 and/or A33 (PRCM, arch timers, A10 timers, etc.) So let's merge everything in separate DTSI, and then, once we have a clear view of what needs what, we will create a common DTSI. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --twlwrnvElrG9k/1g Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVTzXRAAoJEBx+YmzsjxAgj8gQAJuO0eGtdyu+LSp12avsPtwt 8qx8GiJ9JM5zJHL2vrLTfW2ntsYUCDU9b+Z02oevo59giYrBWNSzvkUgsu1RQE0U jrxhL7XuWSXfUXeF4IsnqpZhLStacT+RlZg0H+SDc6hBATO1P42JAwQ8zHRW5UwK xOimGaMtpJ2fYF8kwUgOEB3/N4BMmelQ6K4YPtqlmpB6RjZzZ1uYaRDGtFPztJOP zhqwrQUXv28yVO8HybPSSTZwReparWZyOjn5QS2OpxL91mni0xkoTumPdjOonlKi Gf7Lc6J+esog4NyqGxjrNZUww26Z6KlL5ehkqfVpYDoPTZ/Yhe6jrewx6cL1cjVT A5/GOubBkPaVV+DfwAiTBTDVrhilOrn2sKKTqVQ4mPbLz49ufImQcwQw5s7kocar Vko6+dZfyTPz9eh0EsMMvJ53PJRrrMSWxhSw+h5EH6Knq2f/E/AU9BbYzhcXW3yB cgv8FzMW/5S7zgo7M2V9ay7YCPjGNuo7SHGdqR/3JWWcHYhWa+dP8cR7HW15u0mC /0n1MfTG/Dfk25Ae2WVaf6cJep0M7k3PZyuYkLzvk8J0EatVb/8DM5DxwRvsPR26 pQL+DQg9n7PQ5EE4SDV+A4/qxaIdeih9hOru4Fwiyb/kXpuAlaRrst9qxswLTK4b 7hGPAc6Yh+zprvr6WFM+ =2bSM -----END PGP SIGNATURE----- --twlwrnvElrG9k/1g-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/