Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752963AbbEKGab (ORCPT ); Mon, 11 May 2015 02:30:31 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42131 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752156AbbEKGaZ (ORCPT ); Mon, 11 May 2015 02:30:25 -0400 From: Kalle Valo To: Okash Khawaja Cc: joe@perches.com, linux-wireless@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] adm8211: fix the possible pci cache line sizes inside switch-case References: <20150505224020.GA3805@bytefire-computer> <87wq0ms3mv.fsf@kamboji.qca.qualcomm.com> <20150506063241.GA3042@bytefire-computer> Date: Mon, 11 May 2015 09:30:18 +0300 In-Reply-To: <20150506063241.GA3042@bytefire-computer> (Okash Khawaja's message of "Wed, 6 May 2015 07:32:42 +0100") Message-ID: <87k2wflj7p.fsf@kamboji.qca.qualcomm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2031 Lines: 46 Okash Khawaja writes: > On Wed, May 06, 2015 at 07:59:04AM +0300, Kalle Valo wrote: >> Okash Khawaja writes: >> >> > The PCI cache line size value was being compared against decimal >> > values prefixed with 0x. >> > Fixed the literals to use the correct hex values. >> > >> > Signed-off-by: Okash Khawaja >> [...] >> >> > @@ -1101,10 +1101,10 @@ static void adm8211_hw_init(struct >> > ieee80211_hw *dev) case 0x8: reg |= (0x1 << 14); break; - case >> > 0x16: + case 0x10: reg |= (0x2 << 14); break; - case 0x32: + case >> > 0x20: reg |= (0x3 << 14); break; default: >> Did you test this? How certain can we be that this doesn't break >> anything? >> > > I didn't test it as that would require the hardware that I don't have > at the moment. However, the value in `cline` is PCI cache line size, > which is the CPU's cache line size. It is less likely for cache line > sizes to be 22 or 50, and more likely for them to be 16 or 32. Also, > as far as I understand (and I might be wrong here), cache line size is > used for things like aligning DMA requests with CPU cache line, which > improve performance but wouldn't break anything if the value doesn't > match. In this case, we will fall through to the default case which > leaves `reg` unchanged. > > If there is a way to test it with a mock set up or if you still think > we need to test this on real board, I'll be happy to try get the > hardware. But I will need some guidance around that. Thanks. I don't have any ideas how to test this as I think the hardware is pretty rare nowadays but I think this is safe to commit, thanks for clearing this up. BTW, what you wrote about would have been perferct in the commit log itself. -- Kalle Valo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/