Date: Mon, 11 May 2015 11:14:38 +0200
From: Robert Richter <robert.richter@caviumnetworks.com>
To: Will Deacon <will.deacon@arm.com>
CC: Robert Richter <rric@kernel.org>, Marc Zyngier <Marc.Zyngier@arm.com>,
        Catalin Marinas <Catalin.Marinas@arm.com>,
        Tirumalesh Chalamarla <tchalamarla@cavium.com>,
        Radha Mohan Chintakuntla <rchintakuntla@cavium.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 4/4] arm64: gicv3: its: Increase FORCE_MAX_ZONEORDER for
 Cavium ThunderX
Message-ID: <20150511091438.GW4251@rric.localhost>
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On 05.05.15 11:53:29, Will Deacon wrote:
> On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
> > From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
> > 
> > In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table
> > which is bigger than the allowed max order. So we are forcing it only in
> > case of 4KB page size.
> 
> Does this problem disappear if the ITS driver uses dma_alloc_coherent
> instead? That would also allow us to remove the __flush_dcache_area abuse
> from the driver.

__get_free_pages() is also used internally in dma_alloc_coherent().

There is another case if the device brings dma mem with it. I am not
sure if it would be possible to assign some phys memory via devicetree
to the interrupt controller and then assign that range for its table
allocation.

Another option would be to allocate a hugepage. This would require
setting up hugepages during boottime. I need to figure out whether
that could work.

What about on the remaining 3 patches?

Thanks,

-Robert
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