Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932410AbbELK7j (ORCPT ); Tue, 12 May 2015 06:59:39 -0400 Received: from mail-ob0-f169.google.com ([209.85.214.169]:35154 "EHLO mail-ob0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932192AbbELK7f (ORCPT ); Tue, 12 May 2015 06:59:35 -0400 MIME-Version: 1.0 In-Reply-To: <1430901477-10678-1-git-send-email-gregory.0xf0@gmail.com> References: <1430901477-10678-1-git-send-email-gregory.0xf0@gmail.com> Date: Tue, 12 May 2015 12:59:35 +0200 Message-ID: Subject: Re: [PATCH 0/3] GPIO support for BRCMSTB From: Linus Walleij To: Gregory Fong Cc: "linux-gpio@vger.kernel.org" , Alexandre Courbot , bcm-kernel-feedback-list , Brian Norris , "devicetree@vger.kernel.org" , Florian Fainelli , Ian Campbell , Kumar Gala , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Mark Rutland , Pawel Moll , Rob Herring , Russell King Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1496 Lines: 33 On Wed, May 6, 2015 at 10:37 AM, Gregory Fong wrote: > There is only one IRQ for each GIO IP block (i.e. several register banks share > an IRQ). After briefly looking into the generic IRQ chip implementation, it > seemed like in this case that using it would result in the driver being more > complex than necessary because AFAICT it expects a 1:1 mapping of > irq_chip_generic to gpio_chip. It seemed like less of a pain to have a single > irq_chip since we have a single IRQ for all register banks (multiple > gpio_chips). I might be missing something, maybe using a shared IRQ across > multiple irq_chips is easier than I think? Suggestions welcome. What is needed is a 1:1 mapping between GPIO offsets and IRQ offsets. If you just number your GPIOs 0...n and your IRQs 0...n it should work just fine with one irqchip for all banks. What screws things up is likely that the hardware supports 32 lines per bank and not all are used. I suggest you enable 32 line and 32 IRQs per bank, so that hwirq maps nicely 1:1 on the GPIO offsets, then just use the width thing to NACK operations on GPIO lines you are not using. This way you can also decode and warn on spurious IRQs on the unused lines. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/