Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933508AbbELR0m (ORCPT ); Tue, 12 May 2015 13:26:42 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6538 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933373AbbELR01 (ORCPT ); Tue, 12 May 2015 13:26:27 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 12 May 2015 10:24:05 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , Benson Leung , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Rhyland Klein Subject: [PATCH v5 11/21] clk: tegra: pll: Add code to handle if resets are supported by PLL Date: Tue, 12 May 2015 13:23:54 -0400 Message-ID: <1431451444-23155-13-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1431451444-23155-1-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2540 Lines: 79 From: Bill Huang If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths. Reviewed-by: Benson Leung Signed-off-by: Bill Huang Signed-off-by: Rhyland Klein --- v5: - Added kerneldoc for new members v2: - Moved reset logic to _clk_pll_enable/disable as well drivers/clk/tegra/clk-pll.c | 12 ++++++++++++ drivers/clk/tegra/clk.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 95ad0669291f..54ebab2b85e5 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw) udelay(2); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val &= ~BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + clk_pll_enable_lock(pll); val = pll_readl_base(pll); @@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw) writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val |= BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + if (pll->params->iddq_reg) { val = pll_readl(pll->params->iddq_reg, pll); val |= BIT(pll->params->iddq_bit_idx); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 35ce2a382792..12c3e7edba4c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -176,6 +176,8 @@ struct div_nmp { * @lock_enable_bit_idx: Bit index to enable PLL lock * @iddq_reg: PLL IDDQ register offset * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @reset_reg: Register offset of where RESET bit is + * @reset_bit_idx: Shift of reset bit in reset_reg * @sdm_din_reg: Register offset where SDM settings are * @sdm_din_mask: Mask of SDM divider bits * @sdm_ctrl_reg: Register offset where SDM enable is @@ -239,6 +241,8 @@ struct tegra_clk_pll_params { u32 lock_enable_bit_idx; u32 iddq_reg; u32 iddq_bit_idx; + u32 reset_reg; + u32 reset_bit_idx; u32 sdm_din_reg; u32 sdm_din_mask; u32 sdm_ctrl_reg; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/