Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933530AbbELR0q (ORCPT ); Tue, 12 May 2015 13:26:46 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4468 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933403AbbELR0b (ORCPT ); Tue, 12 May 2015 13:26:31 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 12 May 2015 10:24:49 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , Benson Leung , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Rhyland Klein Subject: [PATCH v5 13/21] clk: tegra: pll: Add support for PLLMB for T210 Date: Tue, 12 May 2015 13:23:56 -0400 Message-ID: <1431451444-23155-15-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1431451444-23155-1-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4698 Lines: 137 Tegra210 SoC's have 2 PLLS for memory usage. Add plumbing to register and handle PLLMB. PLLMB is used to allow switching between 2 PLLM's without having to use and intermediate backup PLL, as we need to lock the PLL before we can switch to it. Signed-off-by: Rhyland Klein --- v3: - Flushed out comment more. v2: - Fixed commit description as suggested. drivers/clk/tegra/clk-pll.c | 46 +++++++++++++++++++++++++++++++++++++++---- drivers/clk/tegra/clk.h | 9 +++++++++ 2 files changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 2b1f672e3bdb..1dfa1433375d 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -561,7 +561,7 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; - if ((params->flags & TEGRA_PLLM) && + if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { val = pll_override_readl(params->pmc_divp_reg, pll); @@ -598,7 +598,7 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; - if ((params->flags & TEGRA_PLLM) && + if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { val = pll_override_readl(params->pmc_divp_reg, pll); @@ -721,8 +721,8 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, if (pll->params->flags & TEGRA_PLL_FIXED) return pll->params->fixed_rate; - /* PLLM is used for memory; we do not change rate */ - if (pll->params->flags & TEGRA_PLLM) + /* PLLM/MB are used for memory; we do not change rate */ + if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) return __clk_get_rate(hw->clk); if (_get_table_rate(hw, &cfg, rate, *prate) && @@ -2300,4 +2300,42 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name, return clk; } + +struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, + void __iomem *clk_base, void __iomem *pmc, + unsigned long flags, + struct tegra_clk_pll_params *pll_params, + spinlock_t *lock) +{ + struct tegra_clk_pll *pll; + struct clk *clk, *parent; + unsigned long parent_rate; + + if (!pll_params->pdiv_tohw) + return ERR_PTR(-EINVAL); + + parent = __clk_lookup(parent_name); + if (!parent) { + WARN(1, "parent clk %s of %s must be registered first\n", + name, parent_name); + return ERR_PTR(-EINVAL); + } + + parent_rate = __clk_get_rate(parent); + + pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); + + pll_params->flags |= TEGRA_PLL_BYPASS; + pll_params->flags |= TEGRA_PLLMB; + pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); + if (IS_ERR(pll)) + return ERR_CAST(pll); + + clk = _tegra_clk_register_pll(pll, name, parent_name, flags, + &tegra_clk_pllm_ops); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} #endif diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 74190ab4f579..7ee764e583f9 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -225,6 +225,8 @@ struct div_nmp { * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv * it may be more accurate (especially if SDM present) + * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This + * flag indicated that it is PLLMB. */ struct tegra_clk_pll_params { unsigned long input_min; @@ -281,6 +283,7 @@ struct tegra_clk_pll_params { #define TEGRA_PLL_BYPASS BIT(9) #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) #define TEGRA_MDIV_NEW BIT(11) +#define TEGRA_PLLMB BIT(12) /** * struct tegra_clk_pll - Tegra PLL clock @@ -387,6 +390,12 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); +struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, + void __iomem *clk_base, void __iomem *pmc, + unsigned long flags, + struct tegra_clk_pll_params *pll_params, + spinlock_t *lock); + /** * struct tegra_clk_pll_out - PLL divider down clock * -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/