Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933802AbbELRfe (ORCPT ); Tue, 12 May 2015 13:35:34 -0400 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:20902 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751583AbbELRfZ (ORCPT ); Tue, 12 May 2015 13:35:25 -0400 X-IronPort-AV: E=Sophos;i="5.13,416,1427785200"; d="scan'208";a="64503065" From: Jonathan Richardson To: Mark Brown , Dmitry Torokhov , Anatol Pomazau CC: Jonathan Richardson , Scott Branden , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , , bcm-kernel-feedback-list , Subject: [PATCH 1/2] ARM: dts: Add binding for Broadcom MSPI driver. Date: Tue, 12 May 2015 10:38:12 -0700 Message-ID: <1431452293-16697-2-git-send-email-jonathar@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1431452293-16697-1-git-send-email-jonathar@broadcom.com> References: <1431452293-16697-1-git-send-email-jonathar@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2159 Lines: 60 Signed-off-by: Jonathan Richardson --- .../devicetree/bindings/spi/brcm,mspi-spi.txt | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt diff --git a/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt new file mode 100644 index 0000000..e86a7a0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt @@ -0,0 +1,39 @@ +Broadcom MSPI controller + +The Broadcom MSPI controller is a SPI controller found on various chips such +as Cygnus. + +Required properties: +- compatible: Must be "brcm,mspi-v0". + +- reg: The first register is the physical base address of the MSPI controller. + The second register is the address of the MSPI interrupt control registers. It + is only required for chips that have a separate register set for extended + interrupt control. This is required for Cygnus. + +- interrupts: Interrupt ID of the controller. + +Optional properties: +- clocks: The MSPI reference clock. If not provided then it is assumed a clock + is enabled by default and no control of clock-frequency (see below) is + possible. + +- clock-names: The name of the reference clock. + +- clock-frequency: Desired frequency of the clock. This will set the serial + clock baud rate (SPBR) based on the reference clock frequency. The frequency + of the SPBR is mspi_clk / (2 * SPBR) where SPBR is a value between 1-255 + determined by the desired 'clock-frequency'. If not provided then the default + baud rate of the controller is used. + +Example: + +mspi: mspi@18047200 { + compatible = "brcm,mspi-v0"; + reg = <0x18047200 0x188>, + <0x180473a0 0x1c>; + interrupts = ; + clocks = <&axi41_clk>; + clock-names = "mspi_clk"; + clock-frequency = <12500000>; +}; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/