Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933778AbbEMJfU (ORCPT ); Wed, 13 May 2015 05:35:20 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:35119 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933516AbbEMJfR (ORCPT ); Wed, 13 May 2015 05:35:17 -0400 Date: Wed, 13 May 2015 11:35:12 +0200 From: Thierry Reding To: Lucas Stach Cc: Thomas Gleixner , Jason Cooper , Marc Zyngier , Stephen Warren , Alexandre Courbot , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH] irqchip: tegra: fix wrong data being passed as the irqdomain chip data Message-ID: <20150513093510.GA31316@ulmo.nvidia.com> References: <1431202014-3136-1-git-send-email-dev@lynxeye.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="sdtB3X0nJg68CQEu" Content-Disposition: inline In-Reply-To: <1431202014-3136-1-git-send-email-dev@lynxeye.de> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2543 Lines: 65 --sdtB3X0nJg68CQEu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, May 09, 2015 at 10:06:54PM +0200, Lucas Stach wrote: > The irq chip functions use the irq chipdata directly as the base register > address of the controller, so this should be passed in instead of a point= er > to the array address holding the base address. >=20 > This fixes Tegra20 CPUidle as now the un-/masking of IRQs at the LIC level > works again, but more importantly it fixes the resulting memory corruptio= n. >=20 > Signed-off-by: Lucas Stach > --- > This is an important fix and should go into 4.1. > --- > drivers/irqchip/irq-tegra.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) This does indeed fix a boot regression on Tegra20. Unfortunately this is not exposed on any platform that uses PCIe because PCIe needs to disable the CPUidle LP2 state as a workaround for a hardware bug. However, I was able to reproduce the regression on TrimSlice by disabling PCIe, hence keeping CPUidle LP2 activated. I reproduced with v4.1-rc3 and applying this patch on top restores functionality. Thanks for tracking this down Lucas. I just noticed that Thomas already applied this while I was testing it, but here goes anyway: Tested-by: Thierry Reding Acked-by: Thierry Reding --sdtB3X0nJg68CQEu Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJVUxrLAAoJEN0jrNd/PrOhubMP/jlIidBct5nWq6KXvHw1QcH9 WUDuOMlFn/BJiq/R5uL2n9p8Q2B9mWJwBhisDvGCe9xmwl1xUmu5ukekcaHyfrQ0 yEr6elQL05WZc4+3+OIyMOef8fpSLwCbc88IaEXQHoql56go7F7OJtpTPVXQX/bw Lxi5EPjaD91cLzE9tj2mgdp3euLBTX3u4j0yBcOLw1gOKTKe51haFN+i3Uii8yhW uyEJela/4gkdLOEYdoK+nyp+Dg6QmRPuuG5EDF/3kSi7zxu/0D2e9dNrlAqnXDEQ EXlrbXIXA2B1j0XsTn9JTVviXGF5M+K8z4RhZby5hjlyrR3EWavP9GquChRNLciw N6wYoFFNx4bxjTnbCmBYi3D6/9lO7z/4BzzFI3duJ6CR2Y6bKxnjKZWmClPpB2sx oKgmb2FmYmLC7f9CPmjNGVtC1kIilBeRT1gqFpX5E9upgs4S6c6zPZuySU7df158 B32uU/v50vBB+Jb5b1I1EKYsHAMO+Rx6Ukt11QLjEKMb+NWdfsUrntJHqurS/jyo ciCFkD1GIYvJXjiwLNVyPIi73eap0aVAiB1DICnDW1tnEt4NJSC3UkQO6uuCYTuo z/nHVie47SMtQVsIORFVz7IWhZ7mrVfm6yR3eioe6775ftLMevVxuVNgumRpsfXF 58T4ObzHjEW4FWtYeuC1 =8ZHo -----END PGP SIGNATURE----- --sdtB3X0nJg68CQEu-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/