Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934570AbbEMQjU (ORCPT ); Wed, 13 May 2015 12:39:20 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:57931 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754145AbbEMQjN (ORCPT ); Wed, 13 May 2015 12:39:13 -0400 From: Arnd Bergmann To: Maxime Coquelin Cc: Daniel Thompson , Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= , Andreas =?ISO-8859-1?Q?F=E4rber?= , Geert Uytterhoeven , Rob Herring , Philipp Zabel , Linus Walleij , Stefan Agner , Peter Meerwald , Paul Bolle , Peter Hurley , Andy Shevchenko , Chanwoo Choi , Russell King , Daniel Lezcano , Joe Perches , Vladimir Zapolskiy , Lee Jones , Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , "linux-doc@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-serial@vger.kernel.org" , Linux-Arch , "linux-api@vger.kernel.org" , Nicolae Rosia , Kamil Lulko Subject: Re: [PATCH v8 14/16] ARM: dts: Introduce STM32F429 MCU Date: Wed, 13 May 2015 18:37:46 +0200 Message-ID: <2282066.NWoIT9ZyLc@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> <11310179.epfRucfQKB@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:vfAnvE3WMzew4BJqh3unH4CaRYlRkYVJSEK+KdPlR4Hx9HBO29b 3P3D90N9icFYTxsPuyhes6y28jJuId8JRo1/B+uR0jX8lwAMPIG5sbqKABMXBuht9/tHJGy /9RKv6jCwEokjXv3IurJThb50XYNJu1f5zZ0PQPtAWWPFB8t9l9wQtIW1rCkhqTsx9CPBYv i6vSsRcgJT42UKWnXXUgQ== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2427 Lines: 52 On Wednesday 13 May 2015 18:29:05 Maxime Coquelin wrote: > 2015-05-13 17:28 GMT+02:00 Arnd Bergmann : > > On Wednesday 13 May 2015 16:20:34 Daniel Thompson wrote: > >> > >> That would suit me very well (although is the 0x20/0x40 not the 8 that > >> we would need in the middle column). > > > > We don't normally use register offsets in DT. The number 8 here instead > > would indicate block 8, where each block is four bytes wide. Using the > > same index here for reset and clock would also help readability. > > My view is that it makes the bindings usage very complex. > Also, it implies we have a specific compatible for stm32f429, whereas > we didn't need with my earlier proposals. > Indeed, the reset driver will need to know the offset of every reset > registers, because: > 1. The AHB registers start at RCC offset 0x10 (up to 0x18) > 2. The APB registers start at RCC offset 0x20 (up to 0x24). > We have a gap between AHB and APB registers, so how do we map the > index for the block you propose? > Should the gap be considered as a block, or we should skip it? > > I'm afraid it will not be straightforward for a reset user to > understand how to use this bindings. > > Either my v7 or v8 versions would have made possible to use a single > compatible for STM32 series. > If we stick with one of these, we could even think to have a "generic" > reset driver, as it could be compatible with sunxi driver bindings. We should definitely try to use the same compatible string for all of them, and make a binding that is easy to use. I haven't fully understood the requirements for the various parts that are involved here. My understanding so far was that the driver could use the index from the first cell and compute void __iomem *reset_reg = rcc_base + 0x10 + 4 * index; void __iomem *clock_reg = rcc_base + 0x30 + 4 * index; Are there parts that need something else? If the 0x10 offset is different, we probably want a different compatible string, and I'd consider it a different part at that point. If there are chips that do not spread the clock from the reset by exactly 256 bits, we could add a DT property in the rcc node for that. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/