Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965181AbbEMTNZ (ORCPT ); Wed, 13 May 2015 15:13:25 -0400 Received: from mout.kundenserver.de ([212.227.17.24]:54458 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933522AbbEMTNQ (ORCPT ); Wed, 13 May 2015 15:13:16 -0400 From: Arnd Bergmann To: Maxime Coquelin Cc: Daniel Thompson , Uwe =?ISO-8859-1?Q?Kleine=2DK=F6nig?= , Andreas =?ISO-8859-1?Q?F=E4rber?= , Geert Uytterhoeven , Rob Herring , Philipp Zabel , Linus Walleij , Stefan Agner , Peter Meerwald , Paul Bolle , Peter Hurley , Andy Shevchenko , Chanwoo Choi , Russell King , Daniel Lezcano , Joe Perches , Vladimir Zapolskiy , Lee Jones , Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , "linux-doc@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-serial@vger.kernel.org" , Linux-Arch , "linux-api@vger.kernel.org" , Nicolae Rosia , Kamil Lulko Subject: Re: [PATCH v8 14/16] ARM: dts: Introduce STM32F429 MCU Date: Wed, 13 May 2015 21:11:33 +0200 Message-ID: <13641152.Yt4ZI3oT6L@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> <2282066.NWoIT9ZyLc@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:GS97d68OZOpFt1qO23PoPs9qEa/or5UuFvDkwtYWZ90kYdLAhBp CsU8beJA6VOZMCcW2RUhLpoAHE+DvzlyNnRKxoevCvHjzlYLX7DbMdmnOOe+SzCNoGg4o8k 36fbn7Wn01b/XFlkexD+YNueketLrBdBJgLAgzDxiLbwvWa2idK3SGaGA0I7t0gOk1ZLlJp R/rJBNAkfnJasFE1ugxMg== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1586 Lines: 41 On Wednesday 13 May 2015 18:54:10 Maxime Coquelin wrote: > This calculation is true, but we have to take into account there is a > hole in the middle, between AHB3, and APB1 register: > > AHB1RSTR : offset = 0x10, index = 0 > AHB2RSTR : offset = 0x14, index = 1 > AHB3RSTR : offset = 0x18, index = 2 > : offset = 0x1c, index = 3 > APB1RSTR : offset = 0x20, index = 4 > APB2RSTR : offset = 0x24, index = 5 > > So we have to carefully document this hole in the bindings, maybe by > listing indexes in the documentation? I would only list the index definitions in the binding if they are common across all chips using that binding. >From what I see above, this is really regular, so it's possible that others follow it as well, but it's also possible that another chip completely screwed up that system because it didn't fit otherwise. Ideally the binding should follow closely what is documented in the data sheet. > > Are there parts that need something else? If the 0x10 offset is > > different, we probably want a different compatible string, and I'd > > consider it a different part at that point. If there are chips > > that do not spread the clock from the reset by exactly 256 bits, > > we could add a DT property in the rcc node for that. > > I will check other chips, to see if this is valid generally. Ok. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/