Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965334AbbEMUgQ (ORCPT ); Wed, 13 May 2015 16:36:16 -0400 Received: from mail-ig0-f182.google.com ([209.85.213.182]:37573 "EHLO mail-ig0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965275AbbEMUgL (ORCPT ); Wed, 13 May 2015 16:36:11 -0400 MIME-Version: 1.0 In-Reply-To: <1431451444-23155-21-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-21-git-send-email-rklein@nvidia.com> Date: Wed, 13 May 2015 13:36:11 -0700 X-Google-Sender-Auth: S0xrQAQwAGLykHfblSrBxLMOI9U Message-ID: Subject: Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic From: Benson Leung To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 944 Lines: 30 On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein wrote: > From: Bill Huang > > Super clock divider control and clock source mux of Tegra210 has changed > a little against prior SoCs, this patch adds Gen5 logic to address those > differences. > > Signed-off-by: Bill Huang It looks like Mikko's and Thierry's EMC changes landed since you rebased : 0c1135f clk: tegra: EMC clock driver depends on EMC driver dc9fdb6 clk: tegra: Add EMC clock driver So v5 doesn't apply cleanly anymore. Could you rebase? > --- > v2: > - Fixed sclk divider address (0x370 -> 0x2c) -- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/