Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934501AbbEMU7o (ORCPT ); Wed, 13 May 2015 16:59:44 -0400 Received: from mail-ie0-f178.google.com ([209.85.223.178]:33488 "EHLO mail-ie0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934262AbbEMU7j (ORCPT ); Wed, 13 May 2015 16:59:39 -0400 MIME-Version: 1.0 In-Reply-To: <1431451444-23155-14-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-14-git-send-email-rklein@nvidia.com> Date: Wed, 13 May 2015 13:59:37 -0700 X-Google-Sender-Auth: 8stznVu3TecXgSVleeizmsX7ILo Message-ID: Subject: Re: [PATCH v5 12/21] clk: tegra: pll: Add specialized logic for T210 From: Benson Leung To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3217 Lines: 90 On Tue, May 12, 2015 at 10:23 AM, Rhyland Klein wrote: > On Tegra210 SoC's, the logic to enable several of the plls is different > from previous generations. Therefore, add registeration functions specific s/registeration/registration > to Tegra210 which will handle them appropriately. > > Signed-off-by: Rhyland Klein > --- > v5: > - Removed unused variables. > > v4: > - Fixed plle_tegra210_is_enabled callback typos > > v2: > - Fixed plle logic. PLLE on Tegra210 has had its enable bit moved, so > we can't use the default _clk_pll_enable/disable routines. Instead, > manually set/clear the correct bit for PLLE within its functions. > > drivers/clk/tegra/clk-pll.c | 347 ++++++++++++++++++++++++++++++++++++++++++- > drivers/clk/tegra/clk.h | 24 +++ > 2 files changed, 369 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > index 54ebab2b85e5..2b1f672e3bdb 100644 > --- a/drivers/clk/tegra/clk-pll.c > +++ b/drivers/clk/tegra/clk-pll.c > @@ -65,6 +65,7 @@ > #define PLLE_BASE_DIVN_WIDTH 8 > #define PLLE_BASE_DIVM_SHIFT 0 > #define PLLE_BASE_DIVM_WIDTH 8 > +#define PLLE_BASE_ENABLE BIT(31) > > #define PLLE_MISC_SETUP_BASE_SHIFT 16 > #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) > @@ -910,7 +911,8 @@ const struct clk_ops tegra_clk_plle_ops = { > > #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ > defined(CONFIG_ARCH_TEGRA_124_SOC) || \ > - defined(CONFIG_ARCH_TEGRA_132_SOC) > + defined(CONFIG_ARCH_TEGRA_132_SOC) || \ > + defined(CONFIG_ARCH_TEGRA_210_SOC) > > static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, > unsigned long parent_rate) > @@ -1579,7 +1581,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, > > #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ > defined(CONFIG_ARCH_TEGRA_124_SOC) || \ > - defined(CONFIG_ARCH_TEGRA_132_SOC) > + defined(CONFIG_ARCH_TEGRA_132_SOC) || \ > + defined(CONFIG_ARCH_TEGRA_210_SOC) > static const struct clk_ops tegra_clk_pllxc_ops = { > .is_enabled = clk_pll_is_enabled, > .enable = clk_pll_enable, It looks like you might have missed changing one set of #if defined further down below to include CONFIG_ARCH_TEGRA_210_SOC : #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) static const struct clk_ops tegra_clk_pllss_ops = { .is_enabled = clk_pll_is_enabled, .enable = clk_pll_enable, .disable = clk_pll_disable, .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, }; struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, struct tegra_clk_pll_params *pll_params, spinlock_t *lock) ... #endif -- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/