Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965645AbbEMW6s (ORCPT ); Wed, 13 May 2015 18:58:48 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:39526 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934327AbbEMW6q (ORCPT ); Wed, 13 May 2015 18:58:46 -0400 Message-ID: <5553D722.1030205@imgtec.com> Date: Wed, 13 May 2015 15:58:42 -0700 From: Leonid Yegoshin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: David Daney CC: , , Subject: Re: [PATCH] MIPS64: 48 bit physaddr support in memory maps References: <20150513185519.27601.4253.stgit@ubuntu-yegoshin> <5553C68C.6000000@gmail.com> In-Reply-To: <5553C68C.6000000@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.20.3.79] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 791 Lines: 22 On 05/13/2015 02:47 PM, David Daney wrote: > On 05/13/2015 11:55 AM, Leonid Yegoshin wrote: >> Originally, it was set to 40bits only but I6400 has 48bits of physaddr. >> > > Why not go to the architectural limit of 59 bits? > Because any physaddr should fit PTE and EntryLo register and we also need 5 or 7 SW bits in PTE. Even with fixed PTE bits layout from http://patchwork.linux-mips.org/patch/7613/ we need 5 or 7 additional bits, so the real limit is 54. And 54 is actually specified as a limit in EntryLo starting from MIPS R2. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/