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Date: Mon, 20 Jan 2003 09:10:50 -0800
From: "Martin J. Bligh" <mbligh@aracnet.com>
To: Ingo Molnar <mingo@elte.hu>, Erich Focht <efocht@ess.nec.de>
cc: Michael Hohnbaum <hohnbaum@us.ibm.com>,
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Subject: Re: [patch] sched-2.5.59-A2
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> or as Arjan points out, like the IBM x440 boxes ...

;-)
 
> i think we want to handle SMT on a different level, ie. via the
> shared-runqueue approach, so it's not a genuine new level of caching, it's
> rather a new concept of multiple logical cores per physical core. (which
> needs is own code in the scheduler.)

Do you have that code working already (presumably needs locking changes)? 
I seem to recall something like that existing already, but I don't recall 
if it was ever fully working or not ...

I think the large PPC64 boxes have multilevel NUMA as well - two real
phys cores on one die, sharing some cache (L2 but not L1? Anton?).
And SGI have multilevel nodes too I think ... so we'll still need 
multilevel NUMA at some point ... but maybe not right now.

M.


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