Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754096AbbENFCQ (ORCPT ); Thu, 14 May 2015 01:02:16 -0400 Received: from e23smtp02.au.ibm.com ([202.81.31.144]:35696 "EHLO e23smtp02.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751004AbbENFCP (ORCPT ); Thu, 14 May 2015 01:02:15 -0400 Date: Thu, 14 May 2015 15:01:07 +1000 From: Gavin Shan To: Alexey Kardashevskiy Cc: linuxppc-dev@lists.ozlabs.org, David Gibson , Benjamin Herrenschmidt , Paul Mackerras , Alex Williamson , Gavin Shan , Wei Yang , linux-kernel@vger.kernel.org Subject: Re: [PATCH kernel v10 26/34] powerpc/powernv/ioda2: Introduce pnv_pci_ioda2_set_window Message-ID: <20150514050107.GA22516@gwshan> Reply-To: Gavin Shan References: <1431358763-24371-1-git-send-email-aik@ozlabs.ru> <1431358763-24371-27-git-send-email-aik@ozlabs.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1431358763-24371-27-git-send-email-aik@ozlabs.ru> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15051405-0005-0000-0000-000001C92731 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3863 Lines: 120 On Tue, May 12, 2015 at 01:39:15AM +1000, Alexey Kardashevskiy wrote: >This is a part of moving DMA window programming to an iommu_ops >callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as >a first parameter (not pnv_ioda_pe) as it is going to be used as >a callback for VFIO DDW code. > >This adds pnv_pci_ioda2_tvt_invalidate() to invalidate TVT as it is >a good thing to do. It does not have immediate effect now as the table >is never recreated after reboot but it will in the following patches. > >This should cause no behavioural change. > >Signed-off-by: Alexey Kardashevskiy >Reviewed-by: David Gibson Reviewed-by: Gavin Shan >--- >Changes: >v9: >* initialize pe->table_group.tables[0] at the very end when >tbl is fully initialized >* moved pnv_pci_ioda2_tvt_invalidate() from earlier patch >--- > arch/powerpc/platforms/powernv/pci-ioda.c | 47 +++++++++++++++++++++++++------ > 1 file changed, 38 insertions(+), 9 deletions(-) > >diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c >index 7d98d83..85f80b2 100644 >--- a/arch/powerpc/platforms/powernv/pci-ioda.c >+++ b/arch/powerpc/platforms/powernv/pci-ioda.c >@@ -1983,6 +1983,43 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, > } > } > >+static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, >+ int num, struct iommu_table *tbl) >+{ >+ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, >+ table_group); >+ struct pnv_phb *phb = pe->phb; >+ int64_t rc; >+ const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; >+ const __u64 win_size = tbl->it_size << tbl->it_page_shift; s/__u64/u64 maybe :-) >+ >+ pe_info(pe, "Setting up window %llx..%llx pg=%x\n", >+ start_addr, start_addr + win_size - 1, >+ 1UL << tbl->it_page_shift); >+ >+ /* >+ * Map TCE table through TVT. The TVE index is the PE number >+ * shifted by 1 bit for 32-bits DMA space. >+ */ >+ rc = opal_pci_map_pe_dma_window(phb->opal_id, >+ pe->pe_number, >+ pe->pe_number << 1, >+ 1, >+ __pa(tbl->it_base), >+ tbl->it_size << 3, >+ 1ULL << tbl->it_page_shift); There is one macro for IOMMU page size: IOMMU_PAGE_SIZE(), which is defined in arch/powerpc/include/asm/iommu.h as below: #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift) >+ if (rc) { >+ pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); >+ return rc; >+ } >+ >+ pnv_pci_link_table_and_group(phb->hose->node, num, >+ tbl, &pe->table_group); >+ pnv_pci_ioda2_tvt_invalidate(pe); >+ >+ return 0; >+} >+ > static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) > { > uint16_t window_id = (pe->pe_number << 1 ) + 1; >@@ -2127,21 +2164,13 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, > pe->table_group.ops = &pnv_pci_ioda2_ops; > #endif > >- /* >- * Map TCE table through TVT. The TVE index is the PE number >- * shifted by 1 bit for 32-bits DMA space. >- */ >- rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, >- pe->pe_number << 1, 1, __pa(tbl->it_base), >- tbl->it_size << 3, 1ULL << tbl->it_page_shift); >+ rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); > if (rc) { > pe_err(pe, "Failed to configure 32-bit TCE table," > " err %ld\n", rc); > goto fail; > } > >- pnv_pci_ioda2_tvt_invalidate(pe); >- > /* OPAL variant of PHB3 invalidated TCEs */ > if (pe->tce_inval_reg) > tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); Thanks, Gavin >-- >2.4.0.rc3.8.gfb3e7d5 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/