Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1945931AbbEOMHd (ORCPT ); Fri, 15 May 2015 08:07:33 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4347 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422728AbbEOMHa (ORCPT ); Fri, 15 May 2015 08:07:30 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 15 May 2015 05:04:57 -0700 From: Bill Huang To: pdeschrijver@nvidia.com CC: mturquette@linaro.org, swarren@wwwdotorg.org, thierry.reding@gmail.com, pwalmsley@nvidia.com, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Bill Huang Subject: [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration Date: Fri, 15 May 2015 20:07:33 +0800 Message-ID: <1431691653-17615-1-git-send-email-bilhuang@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 983 Lines: 32 This fixes two things. - Read the correct IDDQ register - Check the correct IDDQ bit position Signed-off-by: Bill Huang --- drivers/clk/tegra/clk-pll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 05c6d08..734340e 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, val = pll_readl_base(pll); if (val & PLL_BASE_ENABLE) - WARN_ON(val & pll_params->iddq_bit_idx); + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & + BIT(pll_params->iddq_bit_idx)); else { int m; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/