Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751832AbbEQTAs (ORCPT ); Sun, 17 May 2015 15:00:48 -0400 Received: from down.free-electrons.com ([37.187.137.238]:38311 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751296AbbEQTAP (ORCPT ); Sun, 17 May 2015 15:00:15 -0400 Date: Sun, 17 May 2015 16:27:49 +0200 From: Maxime Ripard To: Jens Kuske Cc: Emilio =?iso-8859-1?Q?L=F3pez?= , Mike Turquette , Linus Walleij , Rob Herring , Chen-Yu Tsai , Vishnu Patekar , Hans de Goede , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 06/10] clk: sunxi: Add H3 clocks support Message-ID: <20150517142749.GG4004@lukather> References: <1431707940-19372-1-git-send-email-jenskuske@gmail.com> <1431707940-19372-7-git-send-email-jenskuske@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="MFsiPQgyXjZUSlqD" Content-Disposition: inline In-Reply-To: <1431707940-19372-7-git-send-email-jenskuske@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 7920 Lines: 201 --MFsiPQgyXjZUSlqD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 15, 2015 at 06:38:56PM +0200, Jens Kuske wrote: > The H3 clock control unit is similar to the those of other sun8i family > members like the A23. >=20 > It makes use of the new multiple parents option for the bus gates. > Some of the gates use the new AHB2 clock as parent, whose clock source > is muxable between AHB1 and PLL6/2. The documentation isn't totally clear > about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it > is mostly based on Allwinner kernel source code. >=20 > Signed-off-by: Jens Kuske > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 6 +++ > drivers/clk/sunxi/clk-sunxi.c | 50 +++++++++++++++++= +++++- > 2 files changed, 55 insertions(+), 1 deletion(-) >=20 > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Document= ation/devicetree/bindings/clock/sunxi.txt > index 4fa11af..e367963 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -14,6 +14,7 @@ Required properties: > "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock > "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock > "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 > + "allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3 > "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 > "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock > "allwinner,sun4i-a10-axi-clk" - for the AXI clock > @@ -28,6 +29,7 @@ Required properties: > "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 > "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 > "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 > + "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 > "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 > "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 > "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 > @@ -55,6 +57,7 @@ Required properties: > "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 > "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 > "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 > + "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 > "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 > "allwinner,sun4i-a10-mmc-clk" - for the MMC clock > "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 > @@ -95,6 +98,9 @@ The "allwinner,sun9i-a80-mmc-config-clk" clock also req= uires: > For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate > dummy clocks at 25 MHz and 125 MHz, respectively. See example. > =20 > +For "allwinner,sun8i-h3-bus-gates-clk", the parent clocks shall be > +AHB1, AHB2, APB1 and APB2, in that order. > + > Clock consumers should specify the desired clocks they use with a > "clocks" phandle cell. Consumers that are using a gated clock should > provide an additional ID in their clock property. This ID is the > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c > index afe560c..79364be 100644 > --- a/drivers/clk/sunxi/clk-sunxi.c > +++ b/drivers/clk/sunxi/clk-sunxi.c > @@ -771,6 +771,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data= __initconst =3D { > .shift =3D 12, > }; > =20 > +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst =3D { > + .shift =3D 0, > +}; > + > static void __init sunxi_mux_clk_setup(struct device_node *node, > struct mux_data *data) > { > @@ -886,7 +890,7 @@ static void __init sunxi_divider_clk_setup(struct dev= ice_node *node, > * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks > */ > =20 > -#define SUNXI_GATES_MAX_SIZE 64 > +#define SUNXI_GATES_MAX_SIZE 160 > =20 > struct gates_data { > DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); > @@ -990,6 +994,36 @@ static const struct gates_data sun8i_a23_apb2_gates_= data __initconst =3D { > .mask =3D {0x1F0007}, > }; > =20 > +#define BUS_GATE_PARENT_AHB1 0 > +#define BUS_GATE_PARENT_AHB2 1 > +#define BUS_GATE_PARENT_APB1 2 > +#define BUS_GATE_PARENT_APB2 3 > + > +static const u8 sun8i_h3_bus_gates_parents[] __initconst =3D { > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, > BUS_GATE_PARENT_AHB2, > BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB2, BUS_GATE_PARENT_AHB2, BUS_GATE_PARENT_AHB2, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1, BUS_GATE_PARENT_AHB1, > BUS_GATE_PARENT_APB1, > + BUS_GATE_PARENT_APB1, BUS_GATE_PARENT_APB1, BUS_GATE_PARENT_APB1, > + BUS_GATE_PARENT_APB1, BUS_GATE_PARENT_APB1, BUS_GATE_PARENT_APB1, > + BUS_GATE_PARENT_APB2, BUS_GATE_PARENT_APB2, BUS_GATE_PARENT_APB2, > + BUS_GATE_PARENT_APB2, BUS_GATE_PARENT_APB2, BUS_GATE_PARENT_APB2, > + BUS_GATE_PARENT_APB2, BUS_GATE_PARENT_APB2, > BUS_GATE_PARENT_AHB1, > + BUS_GATE_PARENT_AHB1 > +} I think something like this: if (index < .. || index > ..) clk_parent =3D "ahb1" if (index =3D=3D .. || index < ...) clk_parent =3D "ahb2" etc... Would be both easier to maintain and to read. > + > +static const struct gates_data sun8i_h3_bus_gates_data __initconst =3D { > + .mask =3D {0xffbe6760, 0x00701b39, 0x00007123, 0x001f0007, 0x00000081}, > + .parents =3D sun8i_h3_bus_gates_parents, > +}; > + > static void __init sunxi_gates_clk_setup(struct device_node *node, > struct gates_data *data) > { > @@ -1110,6 +1144,16 @@ static const struct divs_data sun6i_a31_pll6_divs_= data __initconst =3D { > } > }; > =20 > +static const struct divs_data sun8i_h3_pll6_divs_data __initconst =3D { > + .factors =3D &sun6i_a31_pll6_data, > + .ndivs =3D 3, > + .div =3D { > + { .fixed =3D 2 }, /* normal output, pll6 */ > + { .self =3D 1 }, /* base factor clock, pll6 x2 */ > + { .fixed =3D 4 }, /* divided output, pll6 /2 */ > + } > +}; This is exactly the same clock as A31's PLL6, it shouldn't be declared as a different one. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --MFsiPQgyXjZUSlqD Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVWKVlAAoJEBx+YmzsjxAg6F8P/17Yrz5IA1Xu9OXR18GsdKRX loNiO74+WipowtNDAZAICBEeF8SbJ9GnCdOReQmMi4VuPxTNFW3GmfWueuODUNGY EAKPy7/chGdWM3R5fyMnKyqLFuhWsfkn4aHLzvp+5fXYUChdEVU9UuBIjriQj4Zy VqmWl31xWfEM1EavR8qyLA8EfvtZyptJfMHGssmBrL1gWAD5ZSiWgBcC/SESdVa0 3j99wx6cM6WfU1r8lY0NBebUVYlUp1VONyNH+oYm33WRh062+eVnC+M/ATV3qZVg GPho3szhGBmScdmu6buSGrHwqvkTfrSbAaySWoMj2whyGhRQLQfSPJui+PLDR/zk pZTQIRf0VKtzqpYDmefG623CoLOnrPXIWHWKwdF67rg3OcOWjKK0/z9ZQUvPd04e tOXgunqYNkOdk4frpGwTRkczJiUo56bgV2yzPDWyscRYT1uUWRN/EXuMiygIyuh3 RTinHXME4ky1o5+8Z/5v3m2cVFHEsDsSn2ZS2dppHeT5uiQD9X76njdlb/PIhKfk tK2sAHoOsymqF47Wid0XsODxDBnP/9rVuhpa68evTtPP1jqjv/k6EraiY2AANjae t0c23SRWwQGZI2xzJAHRIwabTQ1kAho3oQTS7RsPKLTyTlMSaglos7aLgMNwWnO/ 82CT/Y7MBWzWmMG/QjjN =FAJE -----END PGP SIGNATURE----- --MFsiPQgyXjZUSlqD-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/