Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752470AbbERIHR (ORCPT ); Mon, 18 May 2015 04:07:17 -0400 Received: from mail-bn1bon0058.outbound.protection.outlook.com ([157.56.111.58]:54244 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751223AbbERIG5 (ORCPT ); Mon, 18 May 2015 04:06:57 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Robert.Richter@caviumnetworks.com; Date: Mon, 18 May 2015 10:06:37 +0200 From: Robert Richter To: Alexander Gordeev CC: Robert Richter , Catalin Marinas , Will Deacon , Tejun Heo , Sunil Goutham , Jiang Liu , , , Subject: Re: [PATCH v2] AHCI: Add generic MSI-X interrupt support to SATA PCI driver Message-ID: <20150518080637.GM10428@rric.localhost> References: <1430725538-22162-1-git-send-email-rric@kernel.org> <20150517073331.GA30529@agordeev.usersys.redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150517073331.GA30529@agordeev.usersys.redhat.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-Originating-IP: [92.224.192.210] X-ClientProxiedBy: AMSPR04CA0037.eurprd04.prod.outlook.com (10.242.87.155) To CO2PR0701MB808.namprd07.prod.outlook.com (10.141.246.26) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CO2PR0701MB808; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:CO2PR0701MB808;BCL:0;PCL:0;RULEID:;SRVR:CO2PR0701MB808; X-Forefront-PRVS: 058043A388 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(6009001)(6069001)(24454002)(51704005)(199003)(189002)(189998001)(86362001)(122386002)(47776003)(23726002)(64706001)(4001540100001)(5001860100001)(5001920100001)(81156007)(110136002)(97736004)(5001830100001)(5001960100002)(4001350100001)(76176999)(54356999)(77096005)(62966003)(77156002)(50986999)(106356001)(68736005)(46102003)(66066001)(92566002)(105586002)(46406003)(97756001)(50466002)(83506001)(101416001)(76506005)(33656002)(40100003)(42186005)(2950100001)(87976001)(41533002)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:CO2PR0701MB808;H:rric.localhost;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2015 08:06:52.2924 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR0701MB808 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1636 Lines: 42 On 17.05.15 08:33:32, Alexander Gordeev wrote: > You enable MSI-X for a single chip, but introduce a change to the > generic AHCI code. > > In general MSI-X case, what makes you believe that IRQ vectors are > assigned continuously? > > (Interface ahci_host_activate() kinda expects a contiguous vector > range, but MSI-X does not guarantee that at all). That's the reason why I only enable single interrupt mode which our hardware supports. To not break other chips by this generic code change, there are the following precautions: * Interrupt ranges are not enabled at all. * Only single interrupt mode is enabled for msix cap devices. These devices require a single port only or a total number of int entries less than the total number of ports. In this case only one interrupt will be enabled. * During the discussion with Tejun we agreed to change the init sequence from msix-msi-intx to msi-msix-intx. Thus, if a device offers msi and init does not fail, the msix init code will not be executed. This is equivalent to current code. With this, the code only setups single mode msix as a last resort if msi fails. No interrupt range is enabled at all. Only one interrupt will be enabled. Considering all this I think your concerns are addressed. Also, the code can be easily extended for other devices and thus should be generic from the beginning. -Robert -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/