Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932368AbbERLDB (ORCPT ); Mon, 18 May 2015 07:03:01 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6426 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932349AbbERLCx (ORCPT ); Mon, 18 May 2015 07:02:53 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 18 May 2015 04:00:58 -0700 From: Bill Huang To: pdeschrijver@nvidia.com CC: mturquette@linaro.org, swarren@wwwdotorg.org, thierry.reding@gmail.com, pwalmsley@nvidia.com, rklein@nvidia.com, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Bill Huang Subject: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration Date: Mon, 18 May 2015 19:03:03 +0800 Message-ID: <1431946983-29554-1-git-send-email-bilhuang@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1679 Lines: 50 This fixes bug in tegra_clk_register_pllss() which mistakenly assume the iddq register is the PLL base address. Signed-off-by: Bill Huang --- drivers/clk/tegra/clk-pll.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 05c6d08..f225325 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1826,7 +1826,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, struct clk *clk, *parent; struct tegra_clk_pll_freq_table cfg; unsigned long parent_rate; - u32 val; + u32 val, val_iddq; int i; if (!pll_params->div_nmp) @@ -1874,14 +1874,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); val = pll_readl_base(pll); + val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); if (val & PLL_BASE_ENABLE) { - if (val & BIT(pll_params->iddq_bit_idx)) { + if (val_iddq & BIT(pll_params->iddq_bit_idx)) { WARN(1, "%s is on but IDDQ set\n", name); kfree(pll); return ERR_PTR(-EINVAL); } - } else - val |= BIT(pll_params->iddq_bit_idx); + } else { + val_iddq |= BIT(pll_params->iddq_bit_idx); + writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); + } val &= ~PLLSS_LOCK_OVERRIDE; pll_writel_base(val, pll); -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/