Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755185AbbESAAo (ORCPT ); Mon, 18 May 2015 20:00:44 -0400 Received: from www.linutronix.de ([62.245.132.108]:51758 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754942AbbESAAn (ORCPT ); Mon, 18 May 2015 20:00:43 -0400 Message-Id: <20150518235149.823214798@linutronix.de> User-Agent: quilt/0.63-1 Date: Tue, 19 May 2015 00:00:50 -0000 From: Thomas Gleixner To: LKML Cc: Peter Zijlstra , Vikas Shivappa , x86@kernel.org, Matt Fleming , Will Auld , Kanaka Juvva Subject: [patch 1/6] x86, perf, cqm: Document PQR MSR abuse References: <20150518234114.574556332@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Disposition: inline; filename=x86-perf-cqm-document-PQR-MSR-abuse.patch X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1715 Lines: 50 The cqm code acts like it owns the PQR MSR completely. That's not true because only the lower 10 bits are used for CQM. The upper 32bits are used for CLass Of Service ID (closid). Document the abuse. Will be fixed in a later patch. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/perf_event_intel_cqm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c =================================================================== --- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c +++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c @@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct WARN_ON_ONCE(state->rmid); state->rmid = rmid; - wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); + /* + * This is actually wrong, as the upper 32 bit MSR contain the + * closid which is used for configuring the Cache Allocation + * Technology component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0); raw_spin_unlock_irqrestore(&state->lock, flags); } @@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct if (!--state->cnt) { state->rmid = 0; - wrmsrl(MSR_IA32_PQR_ASSOC, 0); + /* + * This is actually wrong, as the upper 32 bit of the + * MSR contain the closid which is used for + * configuring the Cache Allocation Technology + * component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, 0, 0); } else { WARN_ON_ONCE(!state->rmid); } -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/