Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754379AbbESHzJ (ORCPT ); Tue, 19 May 2015 03:55:09 -0400 Received: from down.free-electrons.com ([37.187.137.238]:50757 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750862AbbESHzE (ORCPT ); Tue, 19 May 2015 03:55:04 -0400 Date: Tue, 19 May 2015 09:53:01 +0200 From: Maxime Ripard To: Jens Kuske Cc: Emilio =?iso-8859-1?Q?L=F3pez?= , Mike Turquette , Linus Walleij , Rob Herring , Chen-Yu Tsai , Vishnu Patekar , Hans de Goede , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates Message-ID: <20150519075301.GT4004@lukather> References: <1431707940-19372-1-git-send-email-jenskuske@gmail.com> <1431707940-19372-3-git-send-email-jenskuske@gmail.com> <20150517125014.GB4004@lukather> <5559ACC6.6050202@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="/cOz769PToeHwu5O" Content-Disposition: inline In-Reply-To: <5559ACC6.6050202@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4415 Lines: 123 --/cOz769PToeHwu5O Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, May 18, 2015 at 11:11:34AM +0200, Jens Kuske wrote: > Hi, >=20 > On 05/17/15 14:50, Maxime Ripard wrote: > > Hi Jens, > >=20 > > On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote: > >> Some newer sunxi SoCs (A83T, H3) don't have individual registers for > >> AHB1, APB1 and APB2 gates anymore, but one big bus gates area where ea= ch > >> gate can have a different parent. > >> > >> The current clock driver sets the same parent for all gates in a group. > >> This commit adds a new parents field to the gates_data structure, which > >> allows us to specify an array of parent indices for every single gate. > >> > >> Signed-off-by: Jens Kuske > >> --- > >> drivers/clk/sunxi/clk-sunxi.c | 12 +++++++++++- > >> 1 file changed, 11 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sun= xi.c > >> index 9a82f17..17cba4d 100644 > >> --- a/drivers/clk/sunxi/clk-sunxi.c > >> +++ b/drivers/clk/sunxi/clk-sunxi.c > >> @@ -898,6 +898,8 @@ static void __init sunxi_divider_clk_setup(struct = device_node *node, > >> =20 > >> struct gates_data { > >> DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); > >> + /* If used, ARRAY_SIZE(parents) has to be >=3D bitmap_weight(mask) */ > >> + const u8 *parents; > >> }; > >> =20 > >> static const struct gates_data sun4i_axi_gates_data __initconst =3D { > >> @@ -1000,16 +1002,21 @@ static void __init sunxi_gates_clk_setup(struc= t device_node *node, > >> struct gates_data *data) > >> { > >> struct clk_onecell_data *clk_data; > >> + const char *parents[SUNXI_MAX_PARENTS]; > >> const char *clk_parent; > >> const char *clk_name; > >> void __iomem *reg; > >> + int npar =3D 0; > >> int qty; > >> int i =3D 0; > >> int j =3D 0; > >> =20 > >> reg =3D of_iomap(node, 0); > >> =20 > >> - clk_parent =3D of_clk_get_parent_name(node, 0); > >> + while (npar < SUNXI_MAX_PARENTS && > >> + (parents[npar] =3D of_clk_get_parent_name(node, npar)) !=3D N= ULL) > >> + npar++; > >> + clk_parent =3D parents[0]; > >> =20 > >> /* Worst-case size approximation and memory allocation */ > >> qty =3D find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); > >> @@ -1026,6 +1033,9 @@ static void __init sunxi_gates_clk_setup(struct = device_node *node, > >> of_property_read_string_index(node, "clock-output-names", > >> j, &clk_name); > >> =20 > >> + if (data->parents && !WARN_ON(data->parents[j] >=3D npar)) > >> + clk_parent =3D parents[data->parents[j]]; > >> + > >=20 > > I'm currently removing that code, so I was more expecting a new > > standalone driver for that clock. >=20 > How do you want to replace that code? To me this looks like a good way > to set up all the different gates sunxi has. By using clock-indices and moving all this gate stuff out of clk-sunxi and into a new driver. It's done already, I just need to make sure everything works at it used to on all the SoCs. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --/cOz769PToeHwu5O Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVWuvdAAoJEBx+YmzsjxAgfwcP/03zoNEKJjPiXV3VlKc2NVKJ 78rw8RF0Fk3CM8qYkOD6/J5SQ+BjOpJxQnhrQiJEui+eB5M33FI9G+obgO/JZfJx ooXlLphRD0m/dKj8mVoduSShiOfyU/K9cbYGTrTcd9vucGGZ9pyaeOztFtdwY29G E0yAMj5sCe7UvkRZ1gPqAIPflV5isrsyZo2lf38zjRM0iygzKWGA8O7HYXfdhtfA aLJclSNyTfTwo/jpWeGhGAle0jZvPg+Y4vQKKJZqr0EX9rS+9MeoSyABdJLQ0GI4 eRevxncDBCZefLi/PIZtBf1QS1jRASIxpj+DGKVZAZxiYZXOfDTIVBJsxrKcT+1O JqrNRL8mUNDQvohu7nzuUwrTe1DcycvxcOdNO5sgMRjddMNeRNwk/T3ijE76/XMO TndB/f3aRrIB3nLYZw1K6xbedf1+gizL+kz/QPLGh4apIK+k1lW2ERYU+xMhkgP7 zhX7uX6DqRJxLws0bgULUt6R8W/BXlDUMU1ffhsC5C3gok9QKnV9/b1uYhHh/ZZk bMnzTR34oo+A1vWOymdjdmBUDjA3Ir8Nzm0M7axINViYoxR3QEuhRuyGigm3CwJL id0eFsiPHei88t/TygbTQn7BBPiiIt5fkoKBeKEhwIIVkcEeSU6b2UMttMm7m8n4 q954B0IZ21NhVcXv66i3 =Z2B0 -----END PGP SIGNATURE----- --/cOz769PToeHwu5O-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/