Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755854AbbESLzD (ORCPT ); Tue, 19 May 2015 07:55:03 -0400 Received: from mail-wg0-f45.google.com ([74.125.82.45]:34834 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752964AbbESLzB (ORCPT ); Tue, 19 May 2015 07:55:01 -0400 Date: Tue, 19 May 2015 12:54:57 +0100 From: Matt Fleming To: Thomas Gleixner Cc: LKML , Peter Zijlstra , Vikas Shivappa , x86@kernel.org, Matt Fleming , Will Auld , Kanaka Juvva Subject: Re: [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state Message-ID: <20150519115457.GF17401@codeblueprint.co.uk> References: <20150518234114.574556332@linutronix.de> <20150518235150.240899319@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150518235150.240899319@linutronix.de> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1800 Lines: 50 On Tue, 19 May, at 12:00:58AM, Thomas Gleixner wrote: > closid (CLass Of Service ID) is used for the Class based Cache > Allocation Technology (CAT). Add explicit storage to the per cpu cache > for it, so it can be used later with the CAT support (requires to move > the per cpu data). > > While at it: > > - Rename the structure to intel_pqr_state which reflects the actual > purpose of the struct: Cache values which go into the PQR MSR > > - Rename 'cnt' to rmid_usecnt which reflects the actual purpose of > the counter. > > - Document the structure and the struct members. > > Signed-off-by: Thomas Gleixner > --- > arch/x86/kernel/cpu/perf_event_intel_cqm.c | 50 +++++++++++++++-------------- > 1 file changed, 27 insertions(+), 23 deletions(-) > > Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c > =================================================================== > --- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c > +++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c > @@ -16,18 +16,32 @@ > static unsigned int cqm_max_rmid = -1; > static unsigned int cqm_l3_scale; /* supposedly cacheline size */ > > -struct intel_cqm_state { > +/** > + * struct intel_pqr_state - State cache for the PQR MSR > + * @rmid: The cached Resource Monitoring ID > + * @closid: The cached Class Of Service ID > + * @usecnt: The usage counter for rmid > + * Typo? Should be @rmid_usecnt. Otherwise, Acked-by: Matt Fleming -- Matt Fleming, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/