Date: Tue, 19 May 2015 15:03:38 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Matt Fleming <matt@codeblueprint.co.uk>
cc: LKML <linux-kernel@vger.kernel.org>, Peter Zijlstra <peterz@infradead.org>,
        Vikas Shivappa <vikas.shivappa@linux.intel.com>, x86@kernel.org,
        Matt Fleming <matt.fleming@intel.com>, Will Auld <will.auld@intel.com>,
        Kanaka Juvva <kanaka.d.juvva@intel.com>
Subject: Re: [patch 2/6] x86, perf, cqm: Use proper data type
In-Reply-To: <20150519085805.GA17401@codeblueprint.co.uk>
Message-ID: <alpine.DEB.2.11.1505191502450.4225@nanos>
References: <20150518234114.574556332@linutronix.de> <20150518235149.919350144@linutronix.de> <20150519085805.GA17401@codeblueprint.co.uk>
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On Tue, 19 May 2015, Matt Fleming wrote:

> On Tue, 19 May, at 12:00:51AM, Thomas Gleixner wrote:
> > int is really not a proper data type for a MSR. Use u32 to make it
> > clear that we are dealing with a 32bit unsigned hardware value.
> > 
> > Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> > ---
> >  arch/x86/kernel/cpu/perf_event_intel_cqm.c |    4 ++--
> >  include/linux/perf_event.h                 |    2 +-
> >  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> Yeah, makes sense, but this is missing a bunch of changes to other
> functions that pass rmids around.

Right. I cared about the stuff which handles the cached state.
 
> Lemme take a swing at that.

Yes, please.

Thanks,

	tglx
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