Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754690AbbETPme (ORCPT ); Wed, 20 May 2015 11:42:34 -0400 Received: from mail-qc0-f177.google.com ([209.85.216.177]:33815 "EHLO mail-qc0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754481AbbETPm3 (ORCPT ); Wed, 20 May 2015 11:42:29 -0400 MIME-Version: 1.0 In-Reply-To: <1430382149-1645-3-git-send-email-jszhang@marvell.com> References: <1430382149-1645-1-git-send-email-jszhang@marvell.com> <1430382149-1645-3-git-send-email-jszhang@marvell.com> Date: Wed, 20 May 2015 21:12:28 +0530 Message-ID: Subject: Re: [PATCH v2 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM From: Pratyush Anand To: Jisheng Zhang Cc: Jingoo Han , Bjorn Helgaas , Minghuan.Lian@freescale.com, fabrice.gasnier@st.com, "linux-pci@vger.kernel.org" , linux-kernel@vger.kernel.org, "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 816 Lines: 18 On Thu, Apr 30, 2015 at 1:52 PM, Jisheng Zhang wrote: > Most transactions' type are cfg0 and MEM, so the Current iATU usage is not > balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors > the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation > ideas comes from Minghuan Lian : > > http://www.spinics.net/lists/linux-pci/msg40440.html > > Signed-off-by: Jisheng Zhang Nice optimization of resources. Thanks :) Acked-by: Pratyush Anand -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/