Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754885AbbETRPv (ORCPT ); Wed, 20 May 2015 13:15:51 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15809 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753241AbbETRPt (ORCPT ); Wed, 20 May 2015 13:15:49 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 20 May 2015 10:13:49 -0700 Message-ID: <555CC142.3010707@nvidia.com> Date: Wed, 20 May 2015 13:15:46 -0400 From: Rhyland Klein User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Bill Huang , CC: , , , , , , Subject: Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration References: <1431946983-29554-1-git-send-email-bilhuang@nvidia.com> In-Reply-To: <1431946983-29554-1-git-send-email-bilhuang@nvidia.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1892 Lines: 55 On 5/18/2015 7:03 AM, Bill Huang wrote: > This fixes bug in tegra_clk_register_pllss() which mistakenly assume the > iddq register is the PLL base address. > > Signed-off-by: Bill Huang > --- > drivers/clk/tegra/clk-pll.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > index 05c6d08..f225325 100644 > --- a/drivers/clk/tegra/clk-pll.c > +++ b/drivers/clk/tegra/clk-pll.c > @@ -1826,7 +1826,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, > struct clk *clk, *parent; > struct tegra_clk_pll_freq_table cfg; > unsigned long parent_rate; > - u32 val; > + u32 val, val_iddq; > int i; > > if (!pll_params->div_nmp) > @@ -1874,14 +1874,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, > pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); > > val = pll_readl_base(pll); > + val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); You could/should likely use pll_readl(pll_params->iddq_reg, pll) here. > if (val & PLL_BASE_ENABLE) { > - if (val & BIT(pll_params->iddq_bit_idx)) { > + if (val_iddq & BIT(pll_params->iddq_bit_idx)) { > WARN(1, "%s is on but IDDQ set\n", name); > kfree(pll); > return ERR_PTR(-EINVAL); > } > - } else > - val |= BIT(pll_params->iddq_bit_idx); > + } else { > + val_iddq |= BIT(pll_params->iddq_bit_idx); > + writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); likewise you can use pll_writel(val_iddq, pll_params->iddq_reg, pll) here. -rhyland -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/