Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753853AbbETW0D (ORCPT ); Wed, 20 May 2015 18:26:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54305 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751962AbbETWZ7 (ORCPT ); Wed, 20 May 2015 18:25:59 -0400 Message-ID: <555D09F3.7020506@codeaurora.org> Date: Wed, 20 May 2015 15:25:55 -0700 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Bintian Wang , mturquette@linaro.org, zhangfei.gao@linaro.org, xuwei5@hisilicon.com, xuejiancheng@huawei.com, tomeu.vizoso@collabora.com, sledge.yanwei@huawei.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, will.deacon@arm.com, robh+dt@kernel.org, khilman@linaro.org, mark.rutland@arm.com, catalin.marinas@arm.com, haojian.zhuang@linaro.org, linux-arm-kernel@lists.infradead.org, olof@lixom.net, yanhaifeng@gmail.com, linux@arm.linux.org.uk, guodong.xu@linaro.org, jorge.ramirez-ortiz@linaro.org, tyler.baker@linaro.org, khilman@kernel.org CC: xuyiping@hisilicon.com, wangbinghui@hisilicon.com, zhenwei.wang@hisilicon.com, victor.lixin@hisilicon.com, puck.chen@hisilicon.com, dan.zhao@hisilicon.com, huxinwei@huawei.com, z.liuxinliang@huawei.com, heyunlei@huawei.com, kong.kongxinwei@hisilicon.com, wangbintian@gmail.com, w.f@huawei.com, liguozhu@hisilicon.com Subject: Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC References: <1432117752-7074-1-git-send-email-bintian.wang@huawei.com> <1432117752-7074-2-git-send-email-bintian.wang@huawei.com> In-Reply-To: <1432117752-7074-2-git-send-email-bintian.wang@huawei.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3477 Lines: 90 On 05/20/15 03:29, Bintian Wang wrote: > Add clock drivers for hi6220 SoC, this driver controls the SoC > registers to supply different clocks to different IPs in the SoC. > > We add one divider clock for hi6220 because the divider in hi6220 > also has a mask bit but it doesnot obey the rule defined by flag > "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by > left shift fixed bits (e.g. 16 bits), so we add this divider clock > to handle it. > > Signed-off-by: Jorge Ramirez-Ortiz > Signed-off-by: Bintian Wang > Acked-by: Haojian Zhuang > Reviewed-by: Zhangfei Gao > Tested-by: Will Deacon > Tested-by: Tyler Baker > --- > drivers/clk/Kconfig | 2 + > drivers/clk/Makefile | 4 +- > drivers/clk/hisilicon/Kconfig | 6 + > drivers/clk/hisilicon/Makefile | 3 +- > drivers/clk/hisilicon/clk-hi6220.c | 291 +++++++++++++++++++++++++++++ > drivers/clk/hisilicon/clk.c | 29 +++ > drivers/clk/hisilicon/clk.h | 17 ++ > drivers/clk/hisilicon/clkdivider-hi6220.c | 156 ++++++++++++++++ > include/dt-bindings/clock/hi6220-clock.h | 173 +++++++++++++++++ > 9 files changed, 677 insertions(+), 4 deletions(-) > create mode 100644 drivers/clk/hisilicon/Kconfig > create mode 100644 drivers/clk/hisilicon/clk-hi6220.c > create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c > create mode 100644 include/dt-bindings/clock/hi6220-clock.h > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 9897f35..18bb930 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706 > ---help--- > This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. > > +source "drivers/clk/hisilicon/Kconfig" > + > source "drivers/clk/qcom/Kconfig" > There's going to be a merge conflict here if this doesn't go through the clk tree. > > + > +static void __init hi6220_clk_sys_init(struct device_node *np) > +{ > + struct hisi_clock_data *clk_data; > + > + clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); > + if (!clk_data) > + return; > + > + hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, > + ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); > + > + hisi_clk_register_mux(hi6220_mux_clks_sys, > + ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); > + > + hi6220_clk_register_divider(hi6220_div_clks_sys, > + ARRAY_SIZE(hi6220_div_clks_sys), clk_data); > + > + if (!clk_data_ao) > + return; > + > + /* enable high speed clock on UART1 mux */ > + clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], > + clk_data_ao->clk_data.clks[HI6220_150M]); Sorry I missed this one earlier. Can we do this clk_set_parent() through assigned-parents instead? I expected an #include for the usage of clk_set_parent() here so I didn't look hard to see if consumer APIs were being used. Otherwise the patch looks fine. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/