Date: Fri, 22 May 2015 15:13:43 +0200
From: Radim =?utf-8?B?S3LEjW3DocWZ?= <rkrcmar@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, bsd@redhat.com
Subject: Re: [PATCH 08/12] KVM: x86: save/load state on SMM switch
Message-ID: <20150522131343.GB31183@potion.brq.redhat.com>
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2015-05-21 22:24+0200, Paolo Bonzini:
> On 21/05/2015 18:33, Radim Krčmář wrote:
> >> > Check the AMD architecture manual.
> > I must be blind, is there more than Table 10-2?
> 
> There's Table 10-1! :DDD

:D  I think I understand ...

10-1 says that amd64 doesn't shift the segment's attributes (they
wouldn't fit into a word otherwise), but table 10-2 says nothing about
the same for ia32 segment registers;  that behavior is model-specific.
Some people on http://www.sandpile.org/x86/smm.htm found out that P6
stores SMM state like this

  7F84h: ES selector
  7F86h: ES access rights
  7F88h: ES limit
  7F8Ch: ES base

which has an extra selector there (makes little sense), but access
rights cannot be shifted for they have only a word of space.

I guess it stems in conflicting online resources, but it's not an
architectural behavior, so we'll be wrong anyway :)
(Not shifting them would make the code a bit nicer ...)
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