Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757634AbbEVSH3 (ORCPT ); Fri, 22 May 2015 14:07:29 -0400 Received: from mail-qk0-f169.google.com ([209.85.220.169]:33380 "EHLO mail-qk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756894AbbEVSHX (ORCPT ); Fri, 22 May 2015 14:07:23 -0400 MIME-Version: 1.0 In-Reply-To: <555F6CE8.1070303@imgtec.com> References: <1432252663-31318-1-git-send-email-ezequiel.garcia@imgtec.com> <1432252663-31318-7-git-send-email-ezequiel.garcia@imgtec.com> <555F6CE8.1070303@imgtec.com> Date: Fri, 22 May 2015 11:07:22 -0700 X-Google-Sender-Auth: 1Hy9stofcu8Fm0FEwnVOi1ulR7M Message-ID: Subject: Re: [PATCH 6/9] clk: pistachio: Propagate rate changes in the MIPS PLL clock sub-tree From: Andrew Bresticker To: Ezequiel Garcia Cc: Linux-MIPS , "linux-kernel@vger.kernel.org" , Mike Turquette , Stephen Boyd , James Hartley , Govindraj Raja , Damien Horsley , Kevin Cernekee , James Hogan Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1992 Lines: 42 On Fri, May 22, 2015 at 10:52 AM, Ezequiel Garcia wrote: > > > On 05/22/2015 02:42 PM, Andrew Bresticker wrote: >> On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia >> wrote: >>> This commit passes CLK_SET_RATE_PARENT to the "mips_div", >>> "mips_internal_div", and "mips_pll_mux" clocks. This flag is needed for the >>> "mips" clock to propagate rate changes up to the "mips_pll" root clock. >>> >>> Signed-off-by: Govindraj Raja >>> Signed-off-by: Ezequiel Garcia >> >> IIRC the clk core will prefer changing a downstream divider over >> propagating the rate change up another level. So, for example, if >> MIPS_PLL is initially 400Mhz and we request a MIPS rate of 200Mhz, >> we'll change the first intermediate divider to /2 rather than >> propagate the rate change up to MIPS_PLL. Wouldn't it be more >> power-efficient to set the MIPS_PLL directly to the requested rate >> rather than using external dividers to divide it down? >> > > Indeed. > > Do you think we still want to be able to change the MIPS clk rate and > propagate the change up to the PLL? Otherwise, I'll drop this patch and > I'll drop the DIV_F and MUX_F macro patches. Well I do think we want to propagate changes from MIPS up to MIPS_PLL, but we need to work around the behavior of CLK_SET_RATE_PARENT when applied to divider clocks. Since there's no reason to ever set the dividers between MIPS and MIPS_PLL to something besides /1 (James/Govindraj/Damien, correct me if I'm wrong here), then I think we could just set CLK_DIVIDER_READ_ONLY on those dividers. It's a bit of a hack, but it's certainly simpler than writing a separate CPU clock driver. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/