Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753299AbbEWEeb (ORCPT ); Sat, 23 May 2015 00:34:31 -0400 Received: from mail-bn1on0066.outbound.protection.outlook.com ([157.56.110.66]:40317 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751486AbbEWEe3 (ORCPT ); Sat, 23 May 2015 00:34:29 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; arm.linux.org.uk; dkim=none (message not signed) header.d=none; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=dinguyen@opensource.altera.com; From: To: CC: , , , , "Dinh Nguyen" Subject: [PATCH 0/3] ARM: socfpga: enable SMP for Arria10 Date: Fri, 22 May 2015 23:28:50 -0500 Message-ID: <1432355333-15515-1-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: SN1PR07CA0038.namprd07.prod.outlook.com (25.162.170.176) To BN3PR03MB1368.namprd03.prod.outlook.com (25.163.34.154) X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1368;2:d1XrXK6GhSqWN30iPAVaeaFyW6qyD1Jhx3+ht1D/3P7NbbE5q3asw82EfhP3Y/1t;2:VO2P2Wf+NubwITYYZZh6lZd9Mcfsz8QpxX9ZIwFcoCn19FMXPuhUQ4/FfR8jsISkhz1HUNcuhot9Ci683BQZROIugxsx+epK4b97RsHjc64GdnAABKXpG4AxqafiRRfEfXgJmSG8Fdm5XVRochG82w==;6:f7O2hbZAF80xdd/K4LMXDYKxw0qCz4H0iaja1yFfEcnK4GruTyr2h2u7GOLr90LK8Y63Qi1bYs6KshbHsaY1U7B31nsAevhO3GruW4V5HX+J5sodgY4wtxmUToQAgQ2JIFgWsHJjw07I1BouenOzlQ==;3:Sb90EiQr9LdE5cZxJJsxAr5Z/x/lDMC6fLNrgv2r4pfufvhDo+Ri19/wJq3pGtWWu0cpFuIaeupEP+003Evd0/v0nB/mhnhson+rtdlh0m++wCDtONTdqTk6HYaGZs1tgHMqRis3vbUVp7lh8hIIvD2yS2z8pA2JznKKOLZ80abYW3mm0XuSGvgUBFL0Zkw5K/j1Q9dUwkhiDn+IOlHXYLEHiA/2REDBGL4R0fGzPI+dqE15/oTFxrarVUDDQH1geY1Vckzd2EgP/CLpGIy/NwexTw6WbqbHsvQZq2oA1O+OU3s5U+oqCrEGOoUlKPLv X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1368;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1500; 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During the process, I found it would be much cleaner to convert the Cyclone5/Arria5 platform to use CPU_METHOD_OF_DECLARE instead of the machine descriptor. The procedure to enable SMP on the Arria10 platform is similar to the Cyclone5/ Arria5 with the exception of a few differences in the register offset of the reset manager designed to bring the secondary core out of reset. So instead of littering the code with machine lookups, just use CPU_METHOD_OF_DECLARE. Thanks, Dinh Nguyen (3): ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: dts: add enable-method property for cpu nodes arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + arch/arm/mach-socfpga/core.h | 2 ++ arch/arm/mach-socfpga/platsmp.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/socfpga.c | 1 - 5 files changed, 36 insertions(+), 1 deletion(-) -- 2.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/