Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759094AbbFBNSb (ORCPT ); Tue, 2 Jun 2015 09:18:31 -0400 Received: from eusmtp01.atmel.com ([212.144.249.243]:57005 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758980AbbFBNSV (ORCPT ); Tue, 2 Jun 2015 09:18:21 -0400 From: Cyrille Pitchen To: , , , CC: , , , , , , , , Cyrille Pitchen Subject: [PATCH v3 0/6] i2c: at91: add support to FIFOs and alternative command Date: Tue, 2 Jun 2015 15:18:30 +0200 Message-ID: X-Mailer: git-send-email 1.8.2.2 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2562 Lines: 60 ChangeLog v3: - fix braces {} coding style issue - split the alternative command patch into 2 patches: the first one fixes a race condition whereas the second one is the actual alternative command patch v2: - fix typo in comment for AT91_TWI_SVEN. - document new device tree bindings like "atmel,fifo-size". - explicitly set the has_alt_cmd boolean to false to already existing chip configs. - use the BIT() macro to define the register bits and do a little cleanup in a dedicated patch. - reword some comments to better explain why the TXCOMP interrupt is no longer enabled in at91_do_twi_transfer() but later in at91_twi_write_data_dma_callback() to avoid a race condition when DMA is used. - remove useless TXCOMP interrupt enable line in at91_twi_write_next_byte() since this interrupt is also enabled by at91_do_twi_transfer() for PIO transfers. v1: This series of patches adds support of two new features which will be introduced with Atmel sama5d2x SoC. First, the alternative command mode eases the sending of STOP conditions. Before starting an I2C transaction, the size data to be transfered is written into the new Alternative Command Register. For each byte transferred, the I2C controller decreases this counter and automatically sends a STOP condition when the counter value reaches 0, that is to say when the last byte of the transaction has been sent/received. So there is no longer need to set the STOP bit into the Control Register. Then the use of FIFOs allows to reduce number I/O accesses: for instance, the TX FIFO allows to write up to 4 data in a single access to the Transmit Holding Register. Also the RX FIFO allows to read up to 4 data in a single access to the Receive Holding Register. Currently only DMA transfers take advantage of FIFOs. Cyrille Pitchen (6): i2c: at91: use BIT() macro to define register bits i2c: at91: update documentation for DT bindings i2c: at91: fix a race condition when using the DMA controller i2c: at91: add support for new alternative command mode i2c: at91: print hardware version i2c: at91: add support to FIFOs Documentation/devicetree/bindings/i2c/i2c-at91.txt | 29 +- drivers/i2c/busses/i2c-at91.c | 354 +++++++++++++++++---- 2 files changed, 321 insertions(+), 62 deletions(-) -- 1.8.2.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/