Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751693AbbFBTl4 (ORCPT ); Tue, 2 Jun 2015 15:41:56 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:32965 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750713AbbFBTlt (ORCPT ); Tue, 2 Jun 2015 15:41:49 -0400 MIME-Version: 1.0 In-Reply-To: References: <1432194944-29087-1-git-send-email-adrian.hunter@intel.com> From: Andy Lutomirski Date: Tue, 2 Jun 2015 12:41:27 -0700 Message-ID: Subject: Re: [PATCH RFC] x86, tsc: Allow for high latency in quick_pit_calibrate() To: Thomas Gleixner Cc: Adrian Hunter , LKML , Linus Torvalds , Andi Kleen , X86 ML , "H. Peter Anvin" , Len Brown Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1095 Lines: 37 On Tue, Jun 2, 2015 at 12:33 PM, Thomas Gleixner wrote: > On Thu, 21 May 2015, Adrian Hunter wrote: > >> If it takes longer than 12us to read the PIT counter lsb/msb, >> then the error margin will never fall below 500ppm within 50ms, >> and Fast TSC calibration will always fail. > > So finally the legacy PIT emulation takes longer than the 30 years old > hardware implementation. Progress! > >> This patch detects when that will happen and switches to using >> a slightly different algorithm that takes advantage of the PIT's >> latch comand. > > Is there really no smarter way to figure out the TSC frequency on > modern systems? I just asked Len this question yesterday. intel_pstate can do it, although the algorithm is a bit gross. --Andy > > Thanks, > > tglx -- Andy Lutomirski AMA Capital Management, LLC -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/