Date: 3 Jun 2015 14:29:36 -0400
Message-ID: <20150603182936.16475.qmail@ns.horizon.com>
From: "George Spelvin" <linux@horizon.com>
To: hpa@zytor.com
Subject: Re: [PATCH RFC] x86, tsc: Allow for high latency in quick_pit_calibrate()
Cc: adrian.hunter@intel.com, ak@linux.intel.com, linux-kernel@vger.kernel.org,
        linux@horizon.com, luto@amacapital.net, tglx@linutronix.de,
        torvalds@linux-foundation.org
In-Reply-To: <20150603062742.19228.qmail@ns.horizon.com>
Sender: linux-kernel-owner@vger.kernel.org
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H. Peter Anvin wrote:
> The RTC is probably the most reliable reference clock, in part because
> 32 kHz crystals are generally calibrated and extremely stable.  However,
> to get more than 1 Hz frequency out of it you have to enable interrupts
> (which gets you to 8192 Hz).

Indeed, it's the only one which is guaranteed a separate crystal.
Many low-cost chipsets generate ALL other frequencies from one crystal
with PLLs.

(This is why I'm keen on using the RTC interrupt for an entropy
source.)

But as I mentioned earlier, you *can* get higher frequencies with
interrupts *or* polling.  When you program the periodic event frequency
(from 2 to 8192 Hz), it does three things at that rate:

1) Periodic interrupts (if enabled),
2) Square wave output (if enabled, and relevant to discrete chips only), and
3) Sets the PE bit (register C, bit 6), which is auto-cleared on read.

So if you're willing to poll the device (which the TSC calibration does
already), you can get high resolution tick edges without interrupts.

Because it's only one read (port 0x71), it's slightly faster than the PIT.

(I also wish we could use all those TSC reads for initial entropy seeding
somehow.)
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