Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752506AbbFKI1P (ORCPT ); Thu, 11 Jun 2015 04:27:15 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:14577 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbbFKI0x (ORCPT ); Thu, 11 Jun 2015 04:26:53 -0400 X-AuditID: cbfec7f5-f794b6d000001495-97-5579464ac842 From: Krzysztof Kozlowski To: Kukjin Kim , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Stephen Boyd , Marek Szyprowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ARM: dts: Fix wrong clock for Exynos4x12 ADC Date: Thu, 11 Jun 2015 17:26:30 +0900 Message-id: <1434011190-24563-2-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> References: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKLMWRmVeSWpSXmKPExsVy+t/xy7pebpWhBu8nKljMP3KO1eL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2Sx9shddounEy6yWRx+085q8eNMN4vFql1/GB14 PC739TJ57Jx1l91j06pONo871/aweWxeUu/Rt2UVo8fnTXIB7FFcNimpOZllqUX6dglcGdcO PWUruMxV0XC6gbGB8TlHFyMnh4SAicTit3MYIWwxiQv31rN1MXJxCAksZZRYt+AkG0hCSOA/ o8T5vcUgNpuAscTm5UvAikQEpjJLLP96mQkkwSxgKPHz3R92EFtYwFHi8SOIZhYBVYndfyYx g9i8Au4S394+YobYJidx8thkVhCbU8BD4tLmv4wQy9wlfl++zjyBkXcBI8MqRtHU0uSC4qT0 XCO94sTc4tK8dL3k/NxNjJDA/LqDcekxq0OMAhyMSjy8FScqQoVYE8uKK3MPMUpwMCuJ8Eab VIYK8aYkVlalFuXHF5XmpBYfYpTmYFES5525632IkEB6YklqdmpqQWoRTJaJg1OqgfHcXd+/ nosty9NTlla29uUG+OdysXFJdjxkORYleWLGt8bchh1rOVTj/zr0rRH+cCb57Pt4k/Tj989J XNrmfae3g1OypkGw3iYuYN+TVX+rdwvEfQw9vHrx01fVLyviP16VOrhtptKGY6cfTH93XG6u XFjUZuZ5S5i1unly/lvWMvx6vjZ+zVslluKMREMt5qLiRABQYqU6SAIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1572 Lines: 41 The TSADC gate clock is present only in Exynos4210. It should not be added to exynos4x12.dtsi because the register controlling it is reserved on Exynos4x12. Instead, the Analog to Digital Converter of Exynos4x12 uses PCLK_ADC gate clock from different register. By using proper clock this effectively enables usage of exynos-adc driver on Exynos4412 boards, enables accessing sensors connected to it on Trats2 board (ntc,ncp15wb473 AP and battery thermistors) and fixes following warnings during boot: [ 2.248247] ERROR: could not get clock /adc@126C0000:adc(0) [ 2.248262] exynos-adc 126c0000.adc: failed getting clock, err = -2 [ 2.248293] exynos-adc: probe of 126c0000.adc failed with error -2 Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index b77dac61ffb5..d7738dd062b7 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -101,7 +101,7 @@ reg = <0x126C0000 0x100>; interrupt-parent = <&combiner>; interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; + clocks = <&clock CLK_PCLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/