Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756495AbbFQNgM (ORCPT ); Wed, 17 Jun 2015 09:36:12 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:31625 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756242AbbFQNgG (ORCPT ); Wed, 17 Jun 2015 09:36:06 -0400 From: Sifan Naeem To: Jonas Gorski CC: Mark Brown , "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Andrew Bresticker Subject: RE: [PATCH v2] spi: img-spfi: Same Edge bit set to double supported transfer speed Thread-Topic: [PATCH v2] spi: img-spfi: Same Edge bit set to double supported transfer speed Thread-Index: AQHQqORGm9gH8JpqV0iTo8UOMexf1p2wiyWAgAAebpA= Date: Wed, 17 Jun 2015 13:36:03 +0000 Message-ID: References: <1434535262-7393-1-git-send-email-sifan.naeem@imgtec.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.167.204] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id t5HDaIlw009772 Content-Length: 2798 Lines: 64 Hi Jonas, > -----Original Message----- > From: Jonas Gorski [mailto:jogo@openwrt.org] > Sent: 17 June 2015 13:12 > To: Sifan Naeem > Cc: Mark Brown; linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; > Andrew Bresticker > Subject: Re: [PATCH v2] spi: img-spfi: Same Edge bit set to double supported > transfer speed > > Hi, > > On Wed, Jun 17, 2015 at 12:01 PM, Sifan Naeem > wrote: > > Same edge bit set in SPFI Control register to double the supported > > spfi clock speed. Setting this bit increases the supported spfi > > frequency from 1/8 to 1/4 of the core clock frequency. > > > > Without this bit set the maximum speed supported was 25MHz on > > Pistachio. > > > > Change-Id: I26782ea88ac3567e72dac11e46c5b5f5f52c5e3d > > Signed-off-by: Sifan Naeem > > --- > > drivers/spi/spi-img-spfi.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c > > index 788e2b1..acce90a 100644 > > --- a/drivers/spi/spi-img-spfi.c > > +++ b/drivers/spi/spi-img-spfi.c > > @@ -40,6 +40,7 @@ > > #define SPFI_CONTROL_SOFT_RESET BIT(11) > > #define SPFI_CONTROL_SEND_DMA BIT(10) > > #define SPFI_CONTROL_GET_DMA BIT(9) > > +#define SPFI_CONTROL_SE BIT(8) > > #define SPFI_CONTROL_TMODE_SHIFT 5 > > #define SPFI_CONTROL_TMODE_MASK 0x7 > > #define SPFI_CONTROL_TMODE_SINGLE 0 > > @@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master > *master, struct spi_device *spi, > > else if (xfer->tx_nbits == SPI_NBITS_QUAD && > > xfer->rx_nbits == SPI_NBITS_QUAD) > > val |= SPFI_CONTROL_TMODE_QUAD << > > SPFI_CONTROL_TMODE_SHIFT; > > + val |= SPFI_CONTROL_SE; > > spfi_writel(spfi, val, SPFI_CONTROL); } > > Don't you also need to update master->max_speed_hz? And if it doubles the > clock speed, don't you need to reflect that in the calculation for the devider? > Currently it looks like it would just cause all transfers to go with the doubled > requested rate. But maybe I'm missing something. > max_speed_hz is already set to 1/4 of the Core clock. So I don't think we need to change that. In Pistachio SoC the max speed of SPFI block is limited to 1/4 of the core clock or to 50Mhz, to achieve these values the change suggested in this patch should have always been set. In the device tree node for SPFI we have to mention the limit of 50Mhz as spi-max-frequency = <50000000>; Thanks, Sifan > > Regards > Jonas ????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?