Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751906AbbFZIpQ (ORCPT ); Fri, 26 Jun 2015 04:45:16 -0400 Received: from foss.arm.com ([217.140.101.70]:59316 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751561AbbFZIpG (ORCPT ); Fri, 26 Jun 2015 04:45:06 -0400 Message-ID: <558D110D.7050000@arm.com> Date: Fri, 26 Jun 2015 09:45:01 +0100 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: Thomas Gleixner , "majun (F)" CC: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "lizefan@huawei.com" , "huxinwei@huawei.com" , dingtianhong , =?UTF-8?B?5ZC05LqR?= , =?UTF-8?B?6LW15L+K5YyW?= , "liguozhu@hisilicon.com" , =?UTF-8?B?6K645aiB?= , chenwei Subject: Re: [PATCH v2 2/3] IRQ/Gic-V3: Change arm-gic-its to support the Mbigen interrupt References: <1434077399-32200-1-git-send-email-majun258@huawei.com> <1434077399-32200-3-git-send-email-majun258@huawei.com> <557E794D.2080705@huawei.com> <558920FF.8030405@huawei.com> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2235 Lines: 57 On 23/06/15 10:29, Thomas Gleixner wrote: > On Tue, 23 Jun 2015, majun (F) wrote: >> 在 2015/6/19 7:52, Thomas Gleixner 写道: >>> On Mon, 15 Jun 2015, majun (F) wrote: >>>> 在 2015/6/12 18:48, Thomas Gleixner 写道: >>>>> Can you please provide a proper description of this mbigen chip and >>>>> explain WHY you think that it needs all this special hackery? >>> >>> You carefully avoided to provide a proper description of this mbigen >>> chip and how it needs to be integrated into the GIC/ITS whatever >>> scenario. >>> >> Mbigen means Message Based Interrupt Generator. >> Its a kind of interrupt controller collects >> the interrupts from external devices and generate msi interrupt. >> >> Mbigen is applied to reduce the number of wire connected interrupts. >> >> As the peripherals increasing, the interrupts lines needed is increasing >> much, especially on the Arm64 server soc. >> >> Therefore, the interrupt pin in gic is not enought for so many perpherals. >> >> Mbigen is designed to fix this problem. >> >> Mbigen chip locates in ITS or outside of ITS. >> >> The working flow of Mbigen shows as below: >> >> external devices ------> MBIGEN ------->ITS >> >> The devices connect to Mbigen chip through wire connecting way. >> Mbigen detects and collectes the interrupts from the these devices. >> >> Then, Mbigen generats the MBI interrupts by writting the ITS >> Translator register. > > So it's nothing else than a non PCI based MSI implementation which > means it can simply use the generic MSI infrastructure and implement a > interrupt domain/chip which implements the MBI specific parts and has > the ITS as its parent domain. > > No hackery in ITS and no extra functionality in the core irq code. It > just can use the existing infrastructure. The only extra you need is a > proper way to retrieve the pointer to the ITS domain. Everything else > just falls in place. I may have a proposal for that. Stay tuned. M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/