Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755637AbbF0BQI (ORCPT ); Fri, 26 Jun 2015 21:16:08 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:47606 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755301AbbF0BJY (ORCPT ); Fri, 26 Jun 2015 21:09:24 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Boris Brezillon , Jonas Andersson Subject: [PATCH 4.0 04/22] clk: at91: pll: fix input range validity check Date: Fri, 26 Jun 2015 18:08:46 -0700 Message-Id: <20150627010854.208581856@linuxfoundation.org> X-Mailer: git-send-email 2.4.4 In-Reply-To: <20150627010854.064848055@linuxfoundation.org> References: <20150627010854.064848055@linuxfoundation.org> User-Agent: quilt/0.64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1792 Lines: 56 4.0-stable review patch. If anyone has any objections, please let me know. ------------------ From: Boris Brezillon commit 6c7b03e1aef2e92176435f4fa562cc483422d20f upstream. The PLL impose a certain input range to work correctly, but it appears that this input range does not apply on the input clock (or parent clock) but on the input clock after it has passed the PLL divisor. Fix the implementation accordingly. Signed-off-by: Boris Brezillon Reported-by: Jonas Andersson Signed-off-by: Greg Kroah-Hartman --- drivers/clk/at91/clk-pll.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(str int i = 0; /* Check if parent_rate is a valid input rate */ - if (parent_rate < characteristics->input.min || - parent_rate > characteristics->input.max) + if (parent_rate < characteristics->input.min) return -ERANGE; /* @@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(str if (!mindiv) mindiv = 1; + if (parent_rate > characteristics->input.max) { + tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max); + if (tmpdiv > PLL_DIV_MAX) + return -ERANGE; + + if (tmpdiv > mindiv) + mindiv = tmpdiv; + } + /* * Calculate the maximum divider which is limited by PLL register * layout (limited by the MUL or DIV field size). -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/