Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752255AbbF1PHk (ORCPT ); Sun, 28 Jun 2015 11:07:40 -0400 Received: from mail-la0-f47.google.com ([209.85.215.47]:36399 "EHLO mail-la0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752244AbbF1PHd (ORCPT ); Sun, 28 Jun 2015 11:07:33 -0400 MIME-Version: 1.0 In-Reply-To: <20150628144529.GZ19530@localhost> References: <1433831736-18253-1-git-send-email-appanad@xilinx.com> <20150622104932.GC19530@localhost> <20150627144054.GW19530@localhost> <20150628144529.GZ19530@localhost> From: Nicolae Rosia Date: Sun, 28 Jun 2015 18:06:52 +0300 Message-ID: Subject: Re: [PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support To: Vinod Koul Cc: Appana Durga Kedareswara Rao , "linux-kernel@vger.kernel.org" , Srikanth Thokala , Michal Simek , Soren Brinkmann , Anirudha Sarangi , "dmaengine@vger.kernel.org" , Punnaiah Choudary Kalluri , "dan.j.williams@intel.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1374 Lines: 27 HI, On Sun, Jun 28, 2015 at 5:45 PM, Vinod Koul wrote: [...] >> > I asked how the device address in configured. For both MM2S S2MM you are >> > using sg for memory address, where are you getting device adress, are you >> > assuming/hardcoding or getting somehow, if so how? >> As the name says, one end is memory (MM) and the other end is an AXI4 >> Stream Bus (S) which has no concept of memory address. >> So yes, it is hardcoded at design time. > So where does the data go at the end of stream bus, who configures that? > Shouldnt all this be at least documented... You make the connection at design time. In Zynq7000 case, there's a dual core Cortex A9 coupled with an FPGA. While designing the FPGA part, you instantiate an Xilinx AXI DMA, on one side you connect it to an AXI4 Lite bus (which is memory mapped) and on the other side you connect your custom peripheral using an AXI4 Stream bus which has no concept of addresses. Here's a picture which depicts all of this [0]. Does this clear things up? [0] http://www.fpgadeveloper.com/wp-content/uploads/2014/08/fpga_developer_20140806_130447.png -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/