Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752401AbbF3KC7 (ORCPT ); Tue, 30 Jun 2015 06:02:59 -0400 Received: from mail-bl2on0147.outbound.protection.outlook.com ([65.55.169.147]:16832 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750821AbbF3KCv (ORCPT ); Tue, 30 Jun 2015 06:02:51 -0400 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Date: Tue, 30 Jun 2015 16:54:09 +0800 From: Zidan Wang To: Charles Keepax CC: , , , , , , Subject: Re: [alsa-devel][PATCH] ASoC: wm8960: update pll and clock setting function Message-ID: <20150630085347.GA22709@shlinux2> References: <5630bd343217e8fa895c5d133497f50739417453.1435316484.git.zidan.wang@freescale.com> <20150629094412.GH6321@opensource.wolfsonmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150629094412.GH6321@opensource.wolfsonmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11FD035;1:hkIaqMZWaCCxRDCajJKkVlyjl9Yjl4gV584XhZ1mWrkcaHfcV+tiGgNBDZdA5CRiDSMIBlb8Q3OLGejD1mzwKW4ds9SzDhueOLkX1nO6Mt+I+o3qZBiP5W7D5CIcnHvjefhb0/ucBamDBndfwG1y4LzgXStDjKZroeA8FjP88dHX9EQ74RfxRcHS6HM/+pYnbs96ATLREtz7zZ/Mcn0wTBZVps8egRh3lm1Ac0MB8+FfJWa3LD1vj/18Qzri+nxz7nH6LuzLBP7w979TPO2GBdb43f4svqon6ZaJ5LC8pUVeFGpXe5WRrfnBrBwkN/Oj+3BcE/T+erlBARYq4M4R8ctkXi8WCReO14PkGo2U/VE= X-Forefront-Antispam-Report: CIP:192.88.158.2;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(1060300003)(2980300002)(339900001)(24454002)(189002)(199003)(164054003)(104016003)(54356999)(50986999)(76176999)(110436001)(106466001)(33656002)(46406003)(33716001)(4290100001)(92566002)(83506001)(50466002)(97756001)(23726002)(87936001)(85426001)(19580395003)(19580405001)(6806004)(5001960100002)(46102003)(110136002)(105606002)(2950100001)(86362001)(62966003)(77156002)(47776003)(4001350100001)(77096005);DIR:OUT;SFP:1102;SCL:1;SRVR:CH1PR03MB610;H:az84smr01.freescale.net;FPR:;SPF:Fail;MLV:sfv;MX:1;A:1;LANG:en; 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In order to support more > > formats and sample rates for a certain MCLK, if snd_soc_dai_set_pll > > failed, it will calculate a available pll out freq and set the pll > > again. > > > > Signed-off-by: Zidan Wang > > --- > > I think this need a little more explaination on how this is > expected to work. From looking at the code what it looks like > what happens is you can set a PLL frequency through set_pll but > then if that frequency doesn't support the sample rate requested > through hw_params it will be changed. This makes me a little > nervous, as something explicitly requested is being overwritten > automatically. > >From RM, we should ensure 5 < PLLN < 13. When i using snd_soc_dai_set_pll to set pll frequency, it's hard for me to get a common pll out frequency. Sometimes, when codec MCLK or sample rate changed, the pll out frequency also should be changed, otherwise set_pll function will be failed. I made it to auto select pll frequency when snd_soc_dai_set_pll failed, so that it can support more sample rate, and don't need to set different pll out frequency for different sample rate and different MCLK. > Would it perhaps be better to allow the auto selection of the > PLL frequency only when things haven't been manually set, or > provide some setting that indicates auto mode? > > Thanks, > Charles -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/