Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752980AbbF3Pnx (ORCPT ); Tue, 30 Jun 2015 11:43:53 -0400 Received: from mga09.intel.com ([134.134.136.24]:25995 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751950AbbF3Pnp (ORCPT ); Tue, 30 Jun 2015 11:43:45 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,378,1432623600"; d="scan'208";a="753354674" From: Jani Nikula To: Daniel Vetter Cc: Ander Conselvan de Oliveira , Dave Airlie , intel-gfx , Linux Kernel Mailing List , DRI mailing list , Daniel Vetter , Linus Torvalds Subject: Re: [Intel-gfx] [PATCH] drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel() In-Reply-To: <20150630142256.GZ30960@phenom.ffwll.local> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <878ub1wdur.fsf@intel.com> <1435669838-24747-1-git-send-email-ander.conselvan.de.oliveira@intel.com> <876165wbol.fsf@intel.com> <20150630142256.GZ30960@phenom.ffwll.local> User-Agent: Notmuch/0.19+112~g77230b0 (http://notmuchmail.org) Emacs/24.4.1 (x86_64-pc-linux-gnu) Date: Tue, 30 Jun 2015 18:41:33 +0300 Message-ID: <87pp4d2ogi.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3999 Lines: 105 On Tue, 30 Jun 2015, Daniel Vetter wrote: > On Tue, Jun 30, 2015 at 04:47:06PM +0300, Jani Nikula wrote: >> On Tue, 30 Jun 2015, Ander Conselvan de Oliveira wrote: >> > Similarly to what is done for SKL, clear the dpll_hw_state of the pipe >> > config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values. >> > That can happen if a crtc that was previously driving an HDMI connector >> > switches to a DP connector. In that case, the wrpll field was left with >> > its old value, leading to warnings like the one below: >> > >> > [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000) >> > ------------[ cut here ]------------ >> > WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]() >> > pipe state doesn't match! >> > >> > This regression was indroduced in >> > >> > commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5 >> > Author: Ander Conselvan de Oliveira >> > Date: Fri May 15 13:34:29 2015 +0300 >> > >> > drm/i915: Don't overwrite (e)DP PLL selection on SKL >> > >> > Signed-off-by: Ander Conselvan de Oliveira >> >> Reported-by: Linus Torvalds >> Tested-by: Jani Nikula > > Yeah makes sense as a fix for 4.2. But for 4.3 I wonder whether the > original commit that started this chain needs to be changed a bit: > > commit 4978cc93d9ac240b435ce60431aef24239b4c270 > Author: Ander Conselvan de Oliveira > Date: Tue Apr 21 17:13:21 2015 +0300 > > drm/i915: Preserve shared DPLL information in new pipe_config > > All the trouble this caused is because it not only preserves the sharing > config (in crtc_state->shared_dpll) but also the ->dpll_hw_state. And I > think with Maarten's latest code (for 4.3) we'd just do an unconditional > compute_config (need it for fast pfit updates and fastboot), which means > the bogus values in ->dpll_hw_state aren't a problem any more since we'll > overwrite them again. And then we could remove that sprinkle of memsets we > have all over, which would be good (since the current approach is > obviously a bit fragile). Anyway: > > Reviewed-by: Daniel Vetter Pushed to drm-intel-next-fixes, thanks for the patch and review. One down, another one left to fix. BR, Jani. > > Thanks, Daniel > >> >> > --- >> > >> > Only compile tested, for the wrpll warning. >> > >> > Thanks, >> > Ander >> > >> > drivers/gpu/drm/i915/intel_dp.c | 3 +++ >> > 1 file changed, 3 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> > index 4ebfc3a..fbd9ac3 100644 >> > --- a/drivers/gpu/drm/i915/intel_dp.c >> > +++ b/drivers/gpu/drm/i915/intel_dp.c >> > @@ -1147,6 +1147,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) >> > static void >> > hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) >> > { >> > + memset(&pipe_config->dpll_hw_state, 0, >> > + sizeof(pipe_config->dpll_hw_state)); >> > + >> > switch (link_bw) { >> > case DP_LINK_BW_1_62: >> > pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; >> > -- >> > 2.1.0 >> > >> >> -- >> Jani Nikula, Intel Open Source Technology Center >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Jani Nikula, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/