Date: Thu, 2 Jul 2015 11:15:20 +0200
From: Ingo Molnar <mingo@kernel.org>
To: Andy Lutomirski <luto@amacapital.net>
Cc: "Brown, Len" <len.brown@intel.com>, Prarit Bhargava <prarit@redhat.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>, Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, X86 ML <x86@kernel.org>,
        "Chandramouli, Dasaratharaman" 
	<dasaratharaman.chandramouli@intel.com>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>,
        Borislav Petkov <bp@alien8.de>, Andy Lutomirski <luto@kernel.org>,
        Denys Vlasenko <dvlasenk@redhat.com>, Brian Gerst <brgerst@gmail.com>,
        Arnaldo Carvalho de Melo <acme@infradead.org>
Subject: Re: [PATCH] x86, msr: Allow read access to /dev/cpu/X/msr
Message-ID: <20150702091520.GA8539@gmail.com>
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* Andy Lutomirski <luto@amacapital.net> wrote:

> On Wed, Jul 1, 2015 at 9:38 AM, Brown, Len <len.brown@intel.com> wrote:
>
> > BTW. I've had a discussion w/ LLNL about their needs, both for security and 
> > performance.  For security, as concluded by this thread, a white list is the 
> > only way to go. I'm thinking a bit-vector of allowed MSR offsets... For 
> > performance, they absolutely can not afford a system call for every single MSR 
> > access.
> 
> I'm surprised.  On a sane kernel, a syscall is about 120 cycles.  Just rdmsr to 
> an unoptimized MSR is probably fifty cycles, I'd guess.

RDMSR to a non-fastpath MSR is more like a hundred cycles:

[  104.151166] x86/bench: ---------------------------
[  104.155350] x86/bench: | Running x86 benchmarks: |
[  104.159530] x86/bench: -------------------------------------------------------------------
[  104.167604] x86/bench: |                 RDTSC-cycles:    hot  (?noise) /   cold  (?noise)
[  104.175870] x86/bench: -------------------------------------------------------------------

Ancient box (10 years old):

               x86/bench: rdmsr                         :     36           /     17  (?29.4%)
               x86/bench: wrmsr                         :    198           /    245

AMD box (2 years old):
...
[  173.208130] x86/bench: rdmsr                         :    121           /    169  (?18.9%)
[  174.633653] x86/bench: wrmsr                         :    365           /    422  (? 9.2%)

Intel box (1 year old):
...
[  130.185195] x86/bench: rdmsr                         :    100           /    112
[  131.263560] x86/bench: wrmsr                         :    492           /    728  (?15.3%)

so the RDMSR cost got progressively worse as MSRs got farther and farther away 
from the core and microcode execution got progressively worse as well.

Thanks,

	Ingo
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