Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753448AbbGCFjB (ORCPT ); Fri, 3 Jul 2015 01:39:01 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:54916 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750960AbbGCFiy (ORCPT ); Fri, 3 Jul 2015 01:38:54 -0400 X-Listener-Flag: 11101 Message-ID: <1435901927.3526.48.camel@mtksdaap41> Subject: Re: [PATCH v2 4/4] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS From: James Liao To: Daniel Kurtz CC: Matthias Brugger , Mike Turquette , Stephen Boyd , srv_heupstream , Ricky Liang , Rob Herring , Sascha Hauer , "open list:OPEN FIRMWARE AND..." , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Date: Fri, 3 Jul 2015 13:38:47 +0800 In-Reply-To: References: <1435633127-31952-1-git-send-email-jamesjj.liao@mediatek.com> <1435633127-31952-5-git-send-email-jamesjj.liao@mediatek.com> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1424 Lines: 41 Hi Daniel, On Wed, 2015-07-01 at 23:22 +0800, Daniel Kurtz wrote: > This looks like 3 separate gate clocks in a chain, with a timing > constraint: USB_LPF must be enabled 100 us after USB_TX. > > 26MHz--> [GATE] --USB_TX--> [LPF] --USB_LPF--> [GATE] --USB_OUT--> > ^ ^ ^ > +--------------+ | | > AP_PLL_CON2.REF2USB_TX_EN -+ | | > AP_PLL_CON2.REF2USB_TX_LPF_EN -+ | > AP_PLL_CON2.REF2USB_TX_OUT_EN --------------------+ > > > I think we can model the gate parts using a proper clock tree model > and the existing clock gate semantics. > I'm not sure the best way to model the delay; but in theory that could > be handled by the clock user (USB driver). Do you mean to create 3 hierarchical clocks (may be clock gates) to model these clocks as the following ? EN -- LPF -- OUT_EN (EN is the parent of LPF, and LPF is the parent of EN) If we model these 3 clocks like above, we can't prevent clock users to enable OUT_EN directly, and there will be no delay between EN and LPF. Or you have other suggestions to model these 3 clcoks? Best regards, James -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/