Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753242AbbGGD5D (ORCPT ); Mon, 6 Jul 2015 23:57:03 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:33144 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753562AbbGGD4t (ORCPT ); Mon, 6 Jul 2015 23:56:49 -0400 MIME-Version: 1.0 X-Originating-IP: [67.161.9.61] In-Reply-To: References: <1436189569-28802-1-git-send-email-jcmvbkbc@gmail.com> <1436189569-28802-8-git-send-email-jcmvbkbc@gmail.com> <20150706134708.GI3644@twins.programming.kicks-ass.net> <20150706140503.GJ3644@twins.programming.kicks-ass.net> Date: Mon, 6 Jul 2015 20:56:48 -0700 Message-ID: Subject: Re: [PATCH 7/8] xtensa: implement counting and sampling perf events From: Chris Zankel To: Max Filippov Cc: Peter Zijlstra , "linux-xtensa@linux-xtensa.org" , LKML , Marc Gauthier , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2706 Lines: 67 Hi Max, We could probably still use NMI with a separate stack. However, for exception handling while in NMI, we might have to implement something similar to x86_64 (https://lwn.net/Articles/484932/). Cheers! -Chris On Mon, Jul 6, 2015 at 7:22 AM, Max Filippov wrote: > On Mon, Jul 6, 2015 at 5:05 PM, Peter Zijlstra wrote: >> On Mon, Jul 06, 2015 at 04:56:09PM +0300, Max Filippov wrote: >>> On Mon, Jul 6, 2015 at 4:47 PM, Peter Zijlstra wrote: >>> > On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote: >>> >> +static int __init xtensa_pmu_init(void) >>> >> +{ >>> >> + int ret; >>> >> + int irq = irq_create_mapping(NULL, XCHAL_PROFILING_INTERRUPT); >>> > >>> > Does this platform have interrupt priorities which you can partially >>> > mask in order to create NMI like behaviour? >>> >>> Not sure what you mean by "NMI like". >> >> There's a number of archs where we implement NMIs by having >> local_irq_disable() only disable part of the interrupt priority range >> and making sure all 'normal' IRQs are mapped in that priority range. >> >> We then map our NMI handlers to a priority above the 'normal' range, >> such that these interrupts can indeed happen when interrupts are >> 'disabled. >> >> See for example: >> >> b4f4372f96e0 ("sparc64: Make %pil level 15 a pseudo-NMI.") >> 0c25e9e6cbe7 ("sparc64: Adjust __raw_local_irq_save() to cooperate in NMIs.") >> c011f80ba091 ("sparc64: Add some more commentary to __raw_local_irq_save()") > > Ok, I see. I guess I can change IRQ disabling logic to not mask perf IRQ > in case it's configured as the only interrupt on its level and it's the highest > medium-level IRQ. > >>> Interrupt priorities are fixed in the current xtensa architecture, and >>> we can in theory mask certain level and below, but practically we >>> always mask all low- and medium- level interrupts. >>> >>> Also we currently can't have handlers for high priority interrupts written in C. >> >> Why not? Surely this can be cured with an assembly stub? > > IIUC that was a deliberate architecture design choice and working around > it penalizes all interrupt handlers. But let me take another close look. > >> The advantage of having NMIs is that profiling information for the >> kernel becomes much more useful. Without this local_irq_enable() will be >> a very 'hot' function. > > I haven't noticed that in my testing. > > -- > Thanks. > -- Max -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/