Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758758AbbGHPbA (ORCPT ); Wed, 8 Jul 2015 11:31:00 -0400 Received: from foss.arm.com ([217.140.101.70]:41807 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932857AbbGHPa7 (ORCPT ); Wed, 8 Jul 2015 11:30:59 -0400 Message-ID: <559D422D.1000307@arm.com> Date: Wed, 08 Jul 2015 16:30:53 +0100 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: Ma Jun , Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "tglx@linutronix.de" , "lizefan@huawei.com" , "huxinwei@huawei.com" , "dingtianhong@huawei.com" , "zhaojunhua@hisilicon.com" , "liguozhu@hisilicon.com" , "xuwei5@hisilicon.com" , "wei.chenwei@hisilicon.com" , "guohanjun@huawei.com" , "wuyun.wu@huawei.com" , "guodong.xu@linaro.org" , "haojian.zhuang@linaro.org" , "zhangfei.gao@linaro.org" , "usman.ahmad@linaro.org" Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> In-Reply-To: <1436166548-34920-2-git-send-email-majun258@huawei.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2484 Lines: 88 Hi, Aside from all the comments Thomas had, the following aspect is worrying me a bit: On 06/07/15 08:09, Ma Jun wrote: > This patch contains the mbigen interrupt controller driver. [...] > +static int mbigen_set_type(struct irq_data *d, unsigned int type) > +{ > + struct mbigen_chip *chip = d->domain->host_data; > + u32 ofst, mask; > + u32 val, nid, hwirq; > + void __iomem *addr; > + > + if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) > + return -EINVAL; You seem to be supporting both edge and level triggered interrupts. Given that the ITS is edge triggered only, I must assume you have some code to regenerate an edge if the wired interrupt is level triggered, and that the line level is still high when you perform the EOI... > + > + nid = GET_NODE_NUM(d->hwirq); > + hwirq = HWIRQ_OFFSET(d->hwirq); > + > + ofst = hwirq / 32 * 4; > + mask = 1 << (hwirq % 32); > + > + addr = chip->base + MBIGEN_TYPE_REG_ADDR(nid, ofst); > + raw_spin_lock(&chip->lock); > + val = readl_relaxed(addr); > + > + if (type == IRQ_TYPE_LEVEL_HIGH) > + val |= mask; > + else if (type == IRQ_TYPE_EDGE_RISING) > + val &= ~mask; > + > + writel_relaxed(val, addr); > + raw_spin_unlock(&chip->lock); > + > + return 0; > +} > + > +static void mbigen_mask_irq(struct irq_data *data) > +{ > + irq_chip_mask_parent(data); > +} > + > +static void mbigen_unmask_irq(struct irq_data *data) > +{ > + irq_chip_unmask_parent(data); > +} > + > +static int mbigen_set_affinity(struct irq_data *data, > + const struct cpumask *mask, > + bool force) > +{ > + int ret; > + > + ret = irq_chip_set_affinity_parent(data, mask, force); > + return ret; > +} > + > +static void mbigen_irq_eoi(struct irq_data *d) > +{ > + irq_chip_eoi_parent(d); ... but this function doesn't have any code dealing with injecting an edge on detecting a level high. So how does it work? Either you're missing some logic here, or you don't really support level interrupts. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/