Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752868AbbGNQ2q (ORCPT ); Tue, 14 Jul 2015 12:28:46 -0400 Received: from mail-bn1on0054.outbound.protection.outlook.com ([157.56.110.54]:58540 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751644AbbGNQ2o (ORCPT ); Tue, 14 Jul 2015 12:28:44 -0400 X-Greylist: delayed 76501 seconds by postgrey-1.27 at vger.kernel.org; Tue, 14 Jul 2015 12:28:44 EDT Authentication-Results: arm.com; dkim=none (message not signed) header.d=none; Message-ID: <55A53509.4060202@caviumnetworks.com> Date: Tue, 14 Jul 2015 09:12:57 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Will Deacon CC: David Daney , "linux-arm-kernel@lists.infradead.org" , Catalin Marinas , "linux-kernel@vger.kernel.org" , Robert Richter , David Daney Subject: Re: [PATCH] arm64: Define HAVE_ARCH_PIO_SIZE and related symbols. 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Systems based on the Cavium ThunderX processor may have up to 8 independent PCIe root complexes. The I/O space on each bus occupies an independent physical address window. So, in order to be able to map all of these (semi) contiguously, we need a lot more virtual address space than is supplied by the default values for all these constants. The option I chose here was to unconditionally expand the I/O ranges for all arm64 systems. If you think this breaks existing systems/drivers, I will have to look for other options. David Daney > AFAICT, mapping an IO bar on arm64 just gives you back a VA into our > PCI_IOBASE region and the ioreadX accessors will just call the readX > macros, so there should be no need for further port adjustment. > > Will > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/