Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753868AbbGNVP5 (ORCPT ); Tue, 14 Jul 2015 17:15:57 -0400 Received: from resqmta-ch2-11v.sys.comcast.net ([69.252.207.43]:53423 "EHLO resqmta-ch2-11v.sys.comcast.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753827AbbGNVPy (ORCPT ); Tue, 14 Jul 2015 17:15:54 -0400 Date: Tue, 14 Jul 2015 16:15:52 -0500 (CDT) From: Christoph Lameter X-X-Sender: cl@east.gentwo.org To: Andy Lutomirski cc: Peter Zijlstra , Chris Mason , "ksummit-discuss@lists.linuxfoundation.org" , "linux-kernel@vger.kernel.org" , Jens Axboe , Mathieu Desnoyers , Shaohua Li Subject: Re: [Ksummit-discuss] [CORE TOPIC] lightweight per-cpu locks / restartable sequences In-Reply-To: Message-ID: References: <20150709190916.GI1522@ret.masoncoding.com> <20150713095757.GW19282@twins.programming.kicks-ass.net> Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 819 Lines: 20 On Tue, 14 Jul 2015, Andy Lutomirski wrote: > Crazy thought: At the risk of proposing something ridiculous, what if > we had per-cpu memory mappings? We could do this at the cost of up to > 2kB of memcpy whenever we switch mms. Expensive but maybe not a > showstopper. This is not crazy and actually was done before. Itanium has that and its doable since the TLB insertion could be handled in software. The problem on x86 is that one would need a separate page table for each processor for each task. There is no way to handle TLB faults in software to my knowledge. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/