Date: Thu, 16 Jul 2015 07:42:14 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Waiman Long <waiman.long@hp.com>
Cc: Ingo Molnar <mingo@redhat.com>, Thomas Gleixner <tglx@linutronix.de>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org, Scott J Norton <scott.norton@hp.com>,
        Douglas Hatch <doug.hatch@hp.com>, Davidlohr Bueso <dave@stgolabs.net>,
        will.deacon@arm.com
Subject: Re: [PATCH v2 1/6] locking/pvqspinlock: Unconditional PV kick with
 _Q_SLOW_VAL
Message-ID: <20150716054214.GU19282@twins.programming.kicks-ass.net>
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On Wed, Jul 15, 2015 at 08:18:23PM -0400, Waiman Long wrote:
> On 07/15/2015 05:10 AM, Peter Zijlstra wrote:
> >  	/*
> >+	 * A failed cmpxchg doesn't provide any memory-ordering guarantees,
> >+	 * so we need a barrier to order the read of the node data in
> >+	 * pv_unhash *after* we've read the lock being _Q_SLOW_VAL.
> >+	 *
> >+	 * Matches the cmpxchg() in pv_wait_head() setting _Q_SLOW_VAL.
> >+	 */
> >+	smp_rmb();
> 
> According to memory_barriers.txt, cmpxchg() is a full memory barrier. It
> didn't say a failed cmpxchg will lose its memory guarantee. So is the
> documentation right? 

The documentation is not entirely clear on this; but there are hints
that this is so.

> Or is that true for some architectures? I think it is
> not true for x86.

On x86 LOCK CMPXCHG is always a sync point, but yes there are archs for
which a failed cmpxchg does _NOT_ provide any barrier semantics.

The reason I started looking was because Will made Argh64 one of those.
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