Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754576AbbGPImp (ORCPT ); Thu, 16 Jul 2015 04:42:45 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:26573 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754422AbbGPImm (ORCPT ); Thu, 16 Jul 2015 04:42:42 -0400 Message-ID: <55A76CBE.2030508@huawei.com> Date: Thu, 16 Jul 2015 16:35:10 +0800 From: "majun (F)" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Marc Zyngier , Thomas Gleixner CC: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "lizefan@huawei.com" , "huxinwei@huawei.com" , "dingtianhong@huawei.com" , "zhaojunhua@hisilicon.com" , "liguozhu@hisilicon.com" , "xuwei5@hisilicon.com" , "wei.chenwei@hisilicon.com" , "guohanjun@huawei.com" , "wuyun.wu@huawei.com" , "guodong.xu@linaro.org" , "haojian.zhuang@linaro.org" , "zhangfei.gao@linaro.org" , "usman.ahmad@linaro.org" Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> <559CA530.2090508@huawei.com> <559D3EB5.4060408@arm.com> In-Reply-To: <559D3EB5.4060408@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.236.124] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A010204.55A76E42.0041,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a75a41876c942284c602b21d499adc85 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1781 Lines: 52 在 2015/7/8 23:16, Marc Zyngier 写道: > On 08/07/15 05:21, majun (F) wrote: >> Hi Thomas: >> [...] >>>> + >>>> + nid = GET_NODE_NUM(d->hwirq); >>>> + ret = get_mbigen_node_type(nid); >>>> + if (ret) >>>> + return 0; >>> >>> Care to explain what this does? It seems for some nodes you cannot >>> write the msi message. So how is that supposed to work? How is that >>> interrupt controlled (mask/unmask ...) ? >>> >> This function is used to write irq event id into vector register.Depends on >> hardware design, write operation is permitted in some mbigen node(nid=0,5,and >7), >> For other mbigen node, this register is read only. > > So how do you expect this to work? You cannot program the event > generated by the mbigen, and the ITS has an ITT that probably doesn't > match your HW. > > Best case, the interrupt is simply dropped, worse case you end up in an > interrupt storm because you can't figure out which device is screaming. > > I'm a bit puzzled. For interrupts connect to mbigen , the interrupt trigger type, device id and event id value are encoded in mbigen chip already. There are two types of mbigen node within a mbigen chip. Type1: event id valud can't be programmed. Type2: event id value can be programmed. For example: An device with 5 interrupts connected to Mbigen node type 1.The default event id vlaue encoded in mbigen chip for these 5 interrupt is from 0 to 4. Because the event id value can't be programmed, we need to define all of 5 interrupts in dts file so that these 5 interrupt has -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/