Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755088AbbGPIw7 (ORCPT ); Thu, 16 Jul 2015 04:52:59 -0400 Received: from foss.arm.com ([217.140.101.70]:42589 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754369AbbGPIw4 (ORCPT ); Thu, 16 Jul 2015 04:52:56 -0400 Message-ID: <55A770E2.2040300@arm.com> Date: Thu, 16 Jul 2015 09:52:50 +0100 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: "majun (F)" , Thomas Gleixner CC: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "lizefan@huawei.com" , "huxinwei@huawei.com" , "dingtianhong@huawei.com" , "zhaojunhua@hisilicon.com" , "liguozhu@hisilicon.com" , "xuwei5@hisilicon.com" , "wei.chenwei@hisilicon.com" , "guohanjun@huawei.com" , "wuyun.wu@huawei.com" , "guodong.xu@linaro.org" , "haojian.zhuang@linaro.org" , "zhangfei.gao@linaro.org" , "usman.ahmad@linaro.org" Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> <559CA530.2090508@huawei.com> <559D3EB5.4060408@arm.com> <55A76CBE.2030508@huawei.com> In-Reply-To: <55A76CBE.2030508@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2447 Lines: 64 On 16/07/15 09:35, majun (F) wrote: > > > 在 2015/7/8 23:16, Marc Zyngier 写道: >> On 08/07/15 05:21, majun (F) wrote: >>> Hi Thomas: >>> > [...] >>>>> + >>>>> + nid = GET_NODE_NUM(d->hwirq); >>>>> + ret = get_mbigen_node_type(nid); >>>>> + if (ret) >>>>> + return 0; >>>> >>>> Care to explain what this does? It seems for some nodes you cannot >>>> write the msi message. So how is that supposed to work? How is that >>>> interrupt controlled (mask/unmask ...) ? >>>> >>> This function is used to write irq event id into vector register.Depends on >>> hardware design, write operation is permitted in some mbigen node(nid=0,5,and >7), >>> For other mbigen node, this register is read only. >> >> So how do you expect this to work? You cannot program the event >> generated by the mbigen, and the ITS has an ITT that probably doesn't >> match your HW. >> >> Best case, the interrupt is simply dropped, worse case you end up in an >> interrupt storm because you can't figure out which device is screaming. >> >> I'm a bit puzzled. > > For interrupts connect to mbigen , the interrupt trigger type, device id and > event id value are encoded in mbigen chip already. > > There are two types of mbigen node within a mbigen chip. > Type1: event id valud can't be programmed. > Type2: event id value can be programmed. > > For example: An device with 5 interrupts connected to Mbigen node > type 1.The default event id vlaue encoded in mbigen chip for these 5 interrupt > is from 0 to 4. > > Because the event id value can't be programmed, we need to define all of > 5 interrupts in dts file so that these 5 interrupt has You can define what you want in the device tree, the ITS doesn't care! Nothing in the ITS code parses this property, and there is absolutely zero chance that the even the ITS has allocated will actually match what you expect. The ITS *relies* on the principle that the evenID can be programmed, just like any MSI controller relies on the device to be programmed with whatever payload has been provided. If all of a sudden we have to support HW that has its own view of the payload, what you have here will simply not work. M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/