Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754384AbbGPJXi (ORCPT ); Thu, 16 Jul 2015 05:23:38 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:56781 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753966AbbGPJXf (ORCPT ); Thu, 16 Jul 2015 05:23:35 -0400 Message-ID: <55A777BD.4080504@huawei.com> Date: Thu, 16 Jul 2015 17:22:05 +0800 From: "majun (F)" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Marc Zyngier , Thomas Gleixner CC: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "lizefan@huawei.com" , "huxinwei@huawei.com" , "dingtianhong@huawei.com" , "zhaojunhua@hisilicon.com" , "liguozhu@hisilicon.com" , "xuwei5@hisilicon.com" , "wei.chenwei@hisilicon.com" , "guohanjun@huawei.com" , "wuyun.wu@huawei.com" , "guodong.xu@linaro.org" , "haojian.zhuang@linaro.org" , "zhangfei.gao@linaro.org" , "usman.ahmad@linaro.org" Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> <559CA530.2090508@huawei.com> <559D3EB5.4060408@arm.com> <55A76CBE.2030508@huawei.com> <55A770E2.2040300@arm.com> In-Reply-To: <55A770E2.2040300@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.236.124] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.55A777D0.0136,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a75a41876c942284c602b21d499adc85 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1712 Lines: 45 在 2015/7/16 16:52, Marc Zyngier 写道: > On 16/07/15 09:35, majun (F) wrote: >>> I'm a bit puzzled. >> >> For interrupts connect to mbigen , the interrupt trigger type, device id and >> event id value are encoded in mbigen chip already. >> >> There are two types of mbigen node within a mbigen chip. >> Type1: event id valud can't be programmed. >> Type2: event id value can be programmed. >> >> For example: An device with 5 interrupts connected to Mbigen node >> type 1.The default event id vlaue encoded in mbigen chip for these 5 interrupt >> is from 0 to 4. >> >> Because the event id value can't be programmed, we need to define all of >> 5 interrupts in dts file so that these 5 interrupt has > > You can define what you want in the device tree, the ITS doesn't care! > Nothing in the ITS code parses this property, and there is absolutely > zero chance that the even the ITS has allocated will actually match what > you expect. > > The ITS *relies* on the principle that the evenID can be programmed, > just like any MSI controller relies on the device to be programmed with > whatever payload has been provided. If all of a sudden we have to > support HW that has its own view of the payload, what you have here will > simply not work. > "If all of a sudden we have to support HW that has its own view of the payload, what you have here will simply not work." I am not very unstand this case, would you please explain this more detail? Thanks! -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/